參數(shù)資料
型號： 16F872
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述： 28引腳，8位閃存微控制器的CMOS
文件頁數(shù)： 9/160頁
文件大?。?/td> 2600K
代理商： 16F872
1999 Microchip Technology Inc.
Preliminary
DS30221A-page 9
PIC16F872
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)
Bank 0
00h
(3)
01h
02h
(3)
03h
(3)
04h
(3)
05h
06h
07h
08h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
PORTA
PORTB
PORTC
—
—
—
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
Unimplemented
--0x 0000
--0u 0000
xxxx xxxx
uuuu uuuu
xxxx xxxx
—
uuuu uuuu
—
09h
0Ah
(1,3)
0Bh
(3)
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
—
Unimplemented
—
—
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
---0 0000
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
—
—
—
—
—
—
ADRESH
(4)
—
ADIF
(4)
(4)
—
(4)
EEIF
SSPIF
BCLIF
CCP1IF
—
TMR2IF
—
TMR1IF
(4)
r0rr 0000
r0rr 0000
-r-0 0--r
-r-0 0--r
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
T1CKPS1
Timer2 module’s register
—
TOUTPS3
TOUTPS2
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
—
—
CCP1X
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
--uu uuuu
0000 0000
0000 0000
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
xxxx xxxx
uuuu uuuu
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
—
—
—
—
—
—
--00 0000
—
—
—
—
—
—
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/
DONE
—
ADON
0000 00-0
0000 00-0
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3:
These registers can be addressed from any bank.
4:
These bits are reserved; always maintain these bits clear.
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