參數(shù)資料
型號： 16F872
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述： 28引腳，8位閃存微控制器的CMOS
文件頁數(shù)： 152/160頁
文件大小： 2600K
代理商： 16F872
PIC16F872
DS30221A-page 152
1999 Microchip Technology Inc.
G
General Call Address Sequence ........................................64
General Call Address Support ...........................................64
General Call Enable bit ......................................................56
I
I/O Ports .............................................................................23
I
2
C ......................................................................................61
I
2
C Master Mode Reception ...............................................73
I
2
C Master Mode Restart Condition ...................................70
I
2
C Mode Selection ............................................................61
I
2
C Module
Acknowledge Sequence timing ..................................75
Addressing .................................................................62
Baud Rate Generator .................................................68
Block Diagram ............................................................66
BRG Block Diagram ...................................................68
BRG Reset due to SDA Collision ...............................80
BRG Timing ...............................................................68
Bus Arbitration ...........................................................78
Bus Collision ..............................................................78
Acknowledge ......................................................78
Restart Condition ...............................................81
Restart Condition Timing (Case1) ......................81
Restart Condition Timing (Case2) ......................81
Start Condition ...................................................79
Start Condition Timing .................................79, 80
Stop Condition ...................................................82
Stop Condition Timing (Case1) ..........................82
Stop Condition Timing (Case2) ..........................82
Transmit Timing .................................................78
Bus Collision timing ....................................................78
Clock Arbitration .........................................................77
Clock Arbitration Timing (Master Transmit) ................77
Conditions to not give ACK Pulse ..............................62
General Call Address Support ...................................64
Master Mode ..............................................................66
Master Mode 7-bit Reception timing ..........................74
Master Mode Operation .............................................67
Master Mode Start Condition .....................................69
Master Mode Transmission ........................................71
Master Mode Transmit Sequence ..............................67
Multi-Master Communication .....................................78
Multi-master Mode .....................................................67
Operation ...................................................................61
Repeat Start Condition timing ....................................70
Slave Mode ................................................................62
Slave Reception .........................................................63
Slave Transmission ....................................................63
SSPBUF .....................................................................62
Stop Condition Receive or Transmit timing ................76
Stop Condition timing .................................................76
Waveforms for 7-bit Reception ..................................63
Waveforms for 7-bit Transmission .............................64
I
2
C Module Address Register, SSPADD ............................62
I
2
C Slave Mode ..................................................................62
ID Locations ...............................................................95, 109
In-Circuit Serial Programming (ICSP) ........................95, 110
INDF ...................................................................................11
INDF Register ..........................................................9, 10, 20
Indirect Addressing ......................................................20, 21
FSR Register ...............................................................7
Instruction Format ............................................................111
Instruction Set .................................................................. 111
ADDLW .................................................................... 113
ADDWF .................................................................... 113
ANDLW .................................................................... 113
ANDWF .................................................................... 113
BCF ......................................................................... 113
BSF .......................................................................... 113
BTFSC ..................................................................... 114
BTFSS ..................................................................... 114
CALL ........................................................................ 114
CLRF ....................................................................... 114
CLRW ...................................................................... 114
CLRWDT ................................................................. 114
COMF ...................................................................... 115
DECF ....................................................................... 115
DECFSZ .................................................................. 115
GOTO ...................................................................... 115
INCF ........................................................................ 115
INCFSZ .................................................................... 115
IORLW ..................................................................... 116
IORWF ..................................................................... 116
MOVF ...................................................................... 116
MOVLW ................................................................... 116
MOVWF ................................................................... 116
NOP ......................................................................... 116
RETFIE .................................................................... 117
RETLW .................................................................... 117
RETURN .................................................................. 117
RLF .......................................................................... 117
RRF ......................................................................... 117
SLEEP ..................................................................... 117
SUBLW .................................................................... 118
SUBWF .................................................................... 118
SWAPF .................................................................... 118
XORLW ................................................................... 118
XORWF ................................................................... 118
Summary Table ....................................................... 112
INTCON ............................................................................. 11
INTCON Register ............................................................... 14
GIE Bit ....................................................................... 14
INTE Bit ..................................................................... 14
INTF Bit ..................................................................... 14
PEIE Bit ..................................................................... 14
RBIE Bit ..................................................................... 14
RBIF Bit ............................................................... 14, 25
T0IE Bit ...................................................................... 14
T0IF Bit ...................................................................... 14
Inter-Integrated Circuit (I
2
C) .............................................. 53
Internal Sampling Switch (Rss) Impedence ....................... 88
Interrupt Sources ....................................................... 95, 105
Block Diagram ......................................................... 105
Interrupt on Change (RB7:RB4 ) ............................... 25
RB0/INT Pin, External .......................................... 6, 106
TMR0 Overflow ........................................................ 106
Interrupts
Bus Collision Interrupt ................................................ 18
Synchronous Serial Port Interrupt .............................. 16
Interrupts, Context Saving During .................................... 106
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ....................... 14, 105
Interrupt on Change (RB7:RB4) Enable
(RBIE Bit) ........................................................... 14, 106
Peripheral Interrupt Enable (PEIE Bit) ....................... 14
RB0/INT Enable (INTE Bit) ........................................ 14
TMR0 Overflow Enable (T0IE Bit) ............................. 14
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