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參數(shù)資料
| 型號(hào)： | 16F872 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT |
| 中文描述： | 28引腳，8位閃存微控制器的CMOS |
| 文件頁(yè)數(shù)： | 70/160頁(yè) |
| 文件大?。?/td> | 2600K |
| 代理商： | 16F872 |
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PIC16F872
DS30221A-page 70
Preliminary
1999 Microchip Technology Inc.
9.2.10
I
2
C MASTER MODE REPEATED START
CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I
2
C mod-
ule is in the idle state. When the RSEN bit is set, the
SCL pin is asserted low. When the SCL pin is sampled
low, the baud rate generator is loaded with the contents
of SSPADD<6:0> and begins counting. The SDA pin is
released (brought high) for one baud rate generator
count (T
BRG
). When the baud rate generator times out
if SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high the baud
rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one T
BRG
. This action is then
followed by assertion of the SDA pin (SDA is low) for
one T
BRG
, while SCL is high. Following this, the RSEN
bit in the SSPCON2 register will be automatically
cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the baud rate generator has timed-out.
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
9.2.10.6
WCOL STATUS FLAG
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-13: REPEAT START CONDITION WAVEFORM
Note 1:
If RSEN is programmed while any other
event is in progress, it will not take effect.
Note 2:
A bus collision during the Repeated Start
condition occurs if:
SDA is sampled low when SCL goes
from low to high.
SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data "1".
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
occurs here.
Write to SSPBUF occurs here.
Falling edge of ninth clock
End of Xmit
At completion of start bit,
hardware clear RSEN bit
and set SSPIF
1st Bit
Set S (SSPSTAT<3>)
T
BRG
T
BRG
SDA = 1,
SCL(no change)
SDA = 1,
SCL = 1
T
BRG
T
BRG
T
BRG
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