參數(shù)資料
型號： 16F872
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述： 28引腳，8位閃存微控制器的CMOS
文件頁數(shù)： 54/160頁
文件大?。?/td> 2600K
代理商： 16F872
PIC16F872
DS30221A-page 54
Preliminary
1999 Microchip Technology Inc.
REGISTER 9-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER
(ADDRESS: 94h)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
bit7
CKE
D/A
P
S
R/W
UA
BF
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit0
bit 7:
SMP
:
Sample bit
SPI Master Mode
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I
2
C master or slave mode:
1
= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0
= Slew rate control enabled for high speed mode (400 kHz)
CKE
: SPI Clock Edge Select (
Figure 9-4
,
Figure 9-5
and
Figure 9-6
)
SPI Mode:
CKP = 0
1
= Transmit happens on transition from active clock state to idle clock state
0
= Transmit happens on transition from idle clock state to active clock state
CKP = 1
1
= Data transmitted on falling edge of SCK
0
= Data transmitted on rising edge of SCK
In I
2
C Master or Slave Mode:
1
= Input levels conform to SMBUS spec
0
= Input levels conform to I
2
C specs
D/A
: Data/Address bit (I
2
C mode only)
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
P
: Stop bit
(I
2
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1
= Indicates that a stop bit has been detected last (this bit is ’0’ on RESET)
0
= Stop bit was not detected last
S
: Start bit
(I
2
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1
= Indicates that a start bit has been detected last (this bit is ’0’ on RESET)
0
= Start bit was not detected last
R/W
: Read/Write bit information (I
2
C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address
match to the next start bit, stop bit or not ACK bit.
In I
2
C slave mode:
1
= Read
0
= Write
In I
2
C master mode:
1
= Transmit is in progress
0
= Transmit is not in progress.
Or’ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode.
UA
: Update Address (10-bit I
2
C mode only)
1
= Indicates that the user needs to update the address in the SSPADD register
0
= Address does not need to be updated
BF
: Buffer Full Status bit
Receive (SPI and I
2
C modes)
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty
Transmit (I
2
C mode only)
1
= Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0
= Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
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