參數(shù)資料
型號(hào)： 16F872
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述： 28引腳，8位閃存微控制器的CMOS
文件頁數(shù)： 55/160頁
文件大?。?/td> 2600K
代理商： 16F872
1999 Microchip Technology Inc.
Preliminary
DS30221A-page 55
PIC16F872
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
bit7
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit0
bit 7:
WCOL
: Write Collision Detect bit
Master Mode:
1
= A write to SSPBUF was attempted while the I
2
C conditions were not valid
0
= No collision
Slave Mode:
1
= SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0
= No collision
SSPOV
: Receive Overflow Indicator bit
In SPI mode
1
= A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow. In
slave mode, the user must read the SSPBUF, even if only transmitting data to avoid overflows. In master
mode, the overflow bit is not set since each operation is initiated by writing to the SSPBUF register. (Must
be cleared in software.)
0
= No overflow
In I
2
C mode
1
= A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in transmit
mode. (Must be cleared in software.)
0
= No overflow
SSPEN
: Synchronous Serial Port Enable bit
In SPI mode, when enabled, these pins must be properly configured as input or output.
1
= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0
= Disables serial port and configures these pins as I/O port pins
In I
2
C mode, when enabled, these pins must be properly configured as input or output.
1
= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0
= Disables serial port and configures these pins as I/O port pins
CKP
: Clock Polarity Select bit
In SPI mode
1
= Idle state for clock is a high level
0
= Idle state for clock is a low level
In I
2
C slave mode, SCK release control
1
= Enable clock
0
= Holds clock low (clock stretch) (Used to ensure data setup time)
In I
2
C master mode
Unused in this mode
SSPM<3:0>
: Synchronous Serial Port Mode Select bits
0000
= SPI master mode, clock = F
OSC
/4
0001
= SPI master mode, clock = F
OSC
/16
0010
= SPI master mode, clock = F
OSC
/64
0011
= SPI master mode, clock = TMR2 output/2
0100
= SPI slave mode, clock = SCK pin. SS pin control enabled.
0101
= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110
= I
2
C slave mode, 7-bit address
0111
= I
2
C slave mode, 10-bit address
1000
= I
2
C master mode, clock = F
OSC
/ (4 * (SSPADD+1) )
1011
= I
2
C firmware controlled master mode (slave idle)
1110
= I
2
C firmware controlled master mode, 7-bit address with start and stop bit interrupts enabled.
1111
= I
2
C firmware controlled master mode, 10-bit address with start and stop bit interrupts enabled.
1001, 1010, 1100, 1101
= reserved
bit 6:
bit 5:
bit 4:
bit 3-0:
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