參數(shù)資料
型號： 16F872
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述： 28引腳，8位閃存微控制器的CMOS
文件頁數(shù)： 49/160頁
文件大?。?/td> 2600K
代理商： 16F872
1999 Microchip Technology Inc.
Preliminary
DS30221A-page 49
PIC16F872
8.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Driven high
Driven low
Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
FIGURE 8-2:
COMPARE MODE OPERATION
BLOCK DIAGRAM
8.2.1
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
CCP PIN CONFIGURATION
8.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
TIMER1 MODE SELECTION
8.2.3
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
SOFTWARE INTERRUPT MODE
8.2.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1 regis-
ter to effectively be a 16-bit programmable period reg-
ister for Timer1.
SPECIAL EVENT TRIGGER
.
8.3
In pulse width modulation mode, the CCP1 pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
PWM Mode (PWM)
Figure 8-3
shows a simplified block diagram of the CCP
module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see
Section 8.3.3
.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
CCPR1H CCPR1L
TMR1H
TMR1L
Comparator
Q
S
R
Output
Logic
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
match
RC2/CCP1
Pin
TRISC<2>
Output Enable
CCP1CON<3:0>
Mode Select
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Note:
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R
Q
S
Duty Cycle Registers
CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1:
8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
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