參數(shù)資料
型號： 16F872
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述： 28引腳，8位閃存微控制器的CMOS
文件頁數(shù)： 61/160頁
文件大?。?/td> 2600K
代理商： 16F872
1999 Microchip Technology Inc.
Preliminary
DS30221A-page 61
PIC16F872
9.2
MSSP I
2
C Operation
The MSSP module in I
2
C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts-on-start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Refer to Application Note AN578, "Use of the SSP
Module in the I
2
C Multi-Master Environment."
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independent of device frequency.
FIGURE 9-5:
I
2
C SLAVE MODE BLOCK
DIAGRAM
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
ured when the I
2
C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>).
The MSSP module has six registers for I
2
C operation.
They are the:
SSP Control Register (SSPCON)
SSP Control Register2 (SSPCON2)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly
accessible
SSP Address Register (SSPADD)
The SSPCON register allows control of the I
2
C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
C modes to be selected:
I
2
C Slave mode (7-bit address)
I
2
C Slave mode (10-bit address)
I
2
C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I
2
C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I
2
C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I
2
C mode.
The CKE bit (SSPSTAT<6:7>) sets the levels of the
SDA and SCL pins in either Master or Slave mode.
When CKE = 1, the levels will conform to the SMBUS
specification. When CKE = 0, the levels will conform to
the I
2
C specification.
Read
Write
SSPSR reg
Match detect
SSPADD reg
Start and
Stop bit detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
SCL
Shift
Clock
MSb
LSb
SDA
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