參數(shù)資料
型號： 16F872
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述： 28引腳，8位閃存微控制器的CMOS
文件頁數(shù)： 140/160頁
文件大小： 2600K
代理商： 16F872
PIC16F872
DS30221A-page 140
Preliminary
1999 Microchip Technology Inc.
FIGURE 14-15: I
2
C BUS DATA TIMING
TABLE 14-8:
I
2
C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
T
HIGH
Clock high time
100 kHz mode
4.0
—
μ
s
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 10 MHz
400 kHz mode
0.6
—
μ
s
SSP Module
100 kHz mode
1.5T
CY
4.7
—
—
101
T
LOW
Clock low time
μ
s
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 10 MHz
400 kHz mode
1.3
—
μ
s
SSP Module
100 kHz mode
400 kHz mode
1.5T
CY
—
20 + 0.1Cb
—
102
T
R
SDA and SCL rise
time
1000
300
ns
ns
Cb is specified to be from
10 to 400 pF
103
T
F
SDA and SCL fall time
100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
90
T
SU
:
STA
START condition
setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
ns
μ
s
μ
s
ns
ns
μ
s
μ
s
91
T
HD
:
STA
START condition hold
time
After this period the first clock
pulse is generated
106
T
HD
:
DAT
Data input hold time
107
T
SU
:
DAT
Data input setup time
Note 2
92
T
SU
:
STO
STOP condition setup
time
109
T
AA
Output valid from
clock
Note 1
110
T
BUF
Bus free time
Time the bus must be free
before a new transmission can
start
Cb
Bus capacitive loading
—
400
pF
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I
2
C-bus device can be used in a standard-mode (100 kHz) I
2
C-bus system, but the requirement tsu;
DAT
≥
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
T
R
max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
2
C bus specification) before the SCL line is
released.
2:
Note:
Refer to Figure 14-3 for load conditions.
90
91
92
100
101
103
106
107
109
109
110
102
SCL
SDA
In
SDA
Out
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