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參數(shù)資料
| 型號(hào)： | 16F872 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT |
| 中文描述： | 28引腳，8位閃存微控制器的CMOS |
| 文件頁(yè)數(shù)： | 31/160頁(yè) |
| 文件大?。?/td> | 2600K |
| 代理商： | 16F872 |
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1999 Microchip Technology Inc.
Preliminary
DS30221A-page 31
PIC16F872
4.3
Reading the Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit RD
(EECON1<0>). The data is available in the very next
instruction cycle of the EEDATA register, therefore it
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is writ-
ten to by the user (during a write operation).
EXAMPLE 4-1:
DATA EEPROM READ
BSF
STATUS, RP1
;
BCF
STATUS, RP0
;Bank 2
MOVLW DATA_EE_ADDR ;
MOVWF EEADR
;Data Memory Address to read
BSF
STATUS, RP0
;Bank 3
BCF
EECON1, EEPGD ;Point to DATA memory
BSF
EECON1, RD
;EEPROM Read
BCF
STATUS, RP0
;Bank 2
MOVF
EEDATA, W
;W = EEDATA
4.4
Writing to the Data EEPROM Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. Then the sequence in
Example 4-2 must be followed to initiate the write cycle.
EXAMPLE 4-2:
DATA EEPROM WRITE
BSF STATUS, RP1 ;
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. EEIF must be cleared by
software.
BCF STATUS, RP0 ; Bank 2
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BSF STATUS, RP0 ; Bank 3
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
SLEEP ; Wait for interrupt to signal write complete
BCF EECON1, WREN ; Disable writes
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