參數(shù)資料
型號： 16F872
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述： 28引腳，8位閃存微控制器的CMOS
文件頁數(shù)： 78/160頁
文件大?。?/td> 2600K
代理商： 16F872
PIC16F872
DS30221A-page 78
Preliminary
1999 Microchip Technology Inc.
9.2.18
MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ’1’ on SDA by letting SDA float high and
another master asserts a ’0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
a bus collision has taken place. The master will set the
Bus Collision Interrupt Flag, BCLIF, and reset the I
2
C
port to its IDLE state. (
Figure 9-19
).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted, and
the SSPBUF can be written to. When the user services
the bus collision interrupt service routine, and if the I
2
C
bus is free, the user can resume communication by
asserting a START condition.
If a START, Repeated Start, STOP or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted, and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision interrupt service routine, and
if the I
2
C bus is free, the user can resume communica-
tion by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of start and stop conditions allows the deter-
mination of when the bus is free. Control of the I
2
C bus
can be taken when the P bit is set in the SSPSTAT reg-
ister, or the bus is idle and the S and P bits are cleared.
FIGURE 9-19: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
by master
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt.
Data changes
while SCL = 0
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