參數(shù)資料
型號: 16F872
廠商: Microchip Technology Inc.
英文描述: CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述: 28引腳,8位閃存微控制器的CMOS
文件頁數(shù): 69/160頁
文件大?。?/td> 2600K
代理商: 16F872
1999 Microchip Technology Inc.
Preliminary
DS30221A-page 69
PIC16F872
9.2.9
I
2
C MASTER MODE START CONDITION
TIMING
To initiate a START condition, the user sets the start
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is re-loaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (T
BRG
), the
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (T
BRG
), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware. The baud rate generator is suspended
leaving the SDA line held low, and the START condition
is complete.
9.2.9.5
WCOL STATUS FLAG
If the user writes the SSPBUF when an START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-12: FIRST START BIT TIMING
Note:
If at the beginning of START condition the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs, the
Bus Collision Interrupt Flag (BCLIF) is set,
the START condition is aborted, and the
I
2
C module is reset into its IDLE state.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
SDA
SCL
S
T
BRG
1st Bit
2nd Bit
T
BRG
SDA = 1,
SCL = 1
At completion of start bit,
Hardware clears SEN bit
and sets SSPIF bit
Write to SSPBUF occurs here
T
BRG
T
BRG
Write to SEN bit occurs here.
Set S bit (SSPSTAT<3>)
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