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參數(shù)資料
| 型號(hào)： | 16F872 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT |
| 中文描述： | 28引腳，8位閃存微控制器的CMOS |
| 文件頁數(shù)： | 43/160頁 |
| 文件大小： | 2600K |
| 代理商： | 16F872 |
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1999 Microchip Technology Inc.
Preliminary
DS30221A-page 43
PIC16F872
6.4
Timer1 Operation in Asynchronous
Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 6.4.1).
In asynchronous counter mode, Timer1 can not be used
as a time-base for capture or compare operations.
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care. Examples
12-2 and 12-3 in the PICmicro
Mid-Range MCU Fam-
ily Reference Manual (DS33023) show how to read and
write Timer1 when it is running in asynchronous mode.
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.6
Resetting Timer1 using CCP1 Trigger
Output
If the CCP1 module is configured in compare mode to
generate a “special event trigger” (CCP1M<3:0> =
1011
), this signal will reset Timer1.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature.
If Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of operation, the CCPR1H:CCPR1L regis-
ter pair effectively becomes the period register for
Timer1.
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 special
event trigger.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Osc Type
LP
Freq
32 kHz
100 kHz
200 kHz
C1
33 pF
15 pF
15 pF
C2
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz
Epson C-001R32.768K-A
100 kHz
Epson C-2 100.00 KC-P
200 kHz
STD XTL 200.000 kHz
Note 1:
Higher capacitance increases the stability of
oscillator, but also increases the start-up time.
2:
Since each resonator/crystal has its own charac-
teristics, the user should consult the resonator/
crystal manufacturer for appropriate values of
external components.
±
20 PPM
±
20 PPM
±
20 PPM
Note:
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
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