
1999 Microchip Technology Inc.
Preliminary
DS30221A-page 51
PIC16F872
TABLE 8-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
TABLE 8-3:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
r0rr 0000
r0rr 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
r0rr 0000
r0rr 0000
87h
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
--uu uuuu
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
Legend:
x
= unknown,
u
= unchanged, r = reserved,
-
= unimplemented read as ’0’. Shaded cells are not used by Capture and
Timer1.
Note 1:
These bits are reserved; always maintain these bits clear.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
r0rr 0000
r0rr 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
r0rr 0000
r0rr 0000
87h
TRISC
PORTC Data Direction Register
1111 1111
1111 1111
11h
TMR2
Timer2 module’s register
0000 0000
0000 0000
92h
PR2
Timer2 module’s period register
1111 1111
1111 1111
12h
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
Legend:
x
= unknown,
u
= unchanged, r = reserved,
-
= unimplemented read as ’0’. Shaded cells are not used by PWM and
Timer2.
Note 1:
These bits are reserved; always maintain these bits clear.