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參數(shù)資料
| 型號(hào)： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 6/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PCI SAR and test/control interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
NC
1, 21,
60, 66,
103–105,
108, 109,
119, 120,
132, 179,
180, 182,
183,
186–189,
192, 193,
197–200
O
No connection. Leave open.
PHYCLK
57
I
PHY-layer clock. PHYCLK is a 19.44-MHz clock signal driven by a PHY-layer clock crystal.
SCANEN
185
I
SCAN enable. Connect to ground for normal operation.
TESTMODE
181
I
Test mode. TESTMODE is driven by the test system. Leave grounded for normal operation.
power and ground
TERMINAL
DESCRIPTION
NAME
NO.
GND
4, 16, 23, 28, 40, 47, 52, 56, 64, 71, 76, 83, 88, 95, 100, 107, 112, 117, 124, 136, 148, 160,
172, 176, 184, 191, 196, 208, 220, 232, 237
Ground
VCC
10, 22, 34, 41, 46, 58, 65, 70, 77, 82, 89, 94, 101, 106, 113, 118, 130, 137, 142, 150, 166,
178, 190, 202, 214, 226, 238
Supply voltage
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