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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 29/49頁 |
| 文件大小： | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
initialization block
The initialization block contains exactly four entries and resides in control memory. The following data shows
the configuration of the initialization block.
initialization block table
PCI-BUS ADDRESS
OFFSET (HEX)
CONTROL MEMORY
ADDRESS (HEX)
BITS 31 – 0
0000
0000
TX completion-ring offset pointer
0004
0001
RX completion-ring offset pointer
0008
0002
Small free-buffer-ring offset pointer
000C
0003
Big free-buffer-ring offset pointer
The PCI-bus address offsets for control memory have the lower-order two address bits always set to zero since
accesses to control memory are permitted only on a word basis. In addition, the driver must write the pointers
to the data structures in the initialization block as follows:
– The transmit completion-ring offset pointer, small free-buffer ring pointer, and big free-buffer ring pointer
are set at 4-byte boundaries. The driver selects a host-memory address and writes it to control memory
by shifting it two bits to the right.
Example: The host address 4EFF0000 (hex) is written to the control-memory initialization block as
13BFC000 (hex).
– The receive completion-ring offset pointer is set at a 16-byte boundary.
This pointer is written by shifting the address four bits to the right.
Example: The host address 4EFF0000 (hex) is written to the control-memory initialization block as
04EFF0000 (hex).
transmit descriptor rings
The TNETA1561 device uses a set of 255 transmit descriptor rings in host memory to manage the 255 transmit
DMA channels. Each ring corresponds to a transmit DMA channel. In addition, each ring holds 256 entries with
each entry corresponding to a buffer. At any time, the TNETA1561 supports 256 buffers per packet; however,
if the software driver can recycle buffers fast enough, it is possible to support more than 256 buffers per packet.
This is accomplished by using four 32-bit word entries per ring entry. These entries contain the control
information for each buffer of a packet that is segmented in a given transmit descriptor ring.
The software driver places the buffer information on a transmit descriptor-ring entry for all the buffers being
queued for transmission. The TNETA1561 fetches each entry to obtain the segmentation information and to
start transmitting ATM cells. The transmit descriptor rings can be assigned to any VPI/VCI combination by
entering the proper VPI/VCI information on the descriptor-ring entries.
The TNETA1561 polls the transmit descriptor ring in a circular fashion looking for entries queued for
transmission. When the PCI SAR reaches an entry that is not queued for transmission, it stops and sends an
idle cell for the given VPI/VCI supported by the transmit descriptor ring. The next time that the PCI SAR returns
to poll this ring, it starts at the place where the entry was not queued for segmentation during the last time the
ring was polled. The order and the frequency at which each descriptor ring is polled is determined by the BWG
table.
The software driver configures the transmit descriptor rings in host memory at 4-byte boundaries and reserves
4K byte per ring. All the control information for the transmit descriptor rings is contained in the following sections.
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