參數(shù)資料
型號(hào)： TNETA1561
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁數(shù)： 22/49頁
文件大?。?/td> 976K
代理商： TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
PCI-bus interface
The PCI-bus interface is provided by the PCIMAC block of the PCI SAR device. The system terminals are for
the PCI-clock and reset function. The address and data terminals are for a 32-bit interface with the least
significant byte (LSB) being the bits (7 – 0) and the most significant byte (MSB) being the bits (31 – 24). The
bus command and byte enable are used to indicate the valid byte of the data. The device fully supports all bus
commands (per PCI local-bus specification. rev 2.0 April 30, 1993) except for the interrupt acknowledge,
special-cycle command, and I/O commands. In the slave mode, the memory-read multiple and the
memory-read lines are treated as the memory-read command. The memory-write and invalidate commands
are treated as the memory-write command. In the master mode, it does not support memory-read multiple and
memory-read line commands. The device also provides all the interface-control terminals; PFRAME PIRDY,
PTRDY, PSTOP, PIDSEL, and PDEVSEL. The PLOCK feature is not supported. For bus-master operation, the
PREQ and PGNT terminals are provided. The error reporting terminal PPERR is for reporting parity errors
(except on a special cycle) and PSSER is for reporting address-and-data parity errors or any other catastrophic
system error. The PCIMAC also generates PSERR when it is self selected as the target.
The PCI SAR keeps track of the number of times it has retried a PCI-master transaction. This feature is
externally programmable up to a maximum of 15 retries. Once the number of retries exceeds this count value,
the TNETA1561 asserts PSERR low. The interrupt PINTA is defined for the PCI SAR. The PCI SAR does not
support any JTAG or boundary-scan function. The PCI SAR implements the following functions: the
PCI-memory bus master for DMA transfers responds as a PCI slave for local-memory accesses and supports
disconnection with retry for PCI. As a PCI-bus master, it supports burst and nonburst data accesses; however,
in slave mode it supports only nonburst data transfers. The PCI SAR is designed to meet the worst-case latency
of the PCI bus up to 30
μ
s. A minimum bus-grant value ensures the PCI-bus access for a minimum duration
that is long enough to transfer a cell (48 bytes). The PCI macro terminates a transaction when the TNETA1561
is acting as a bus master and no device-select return is detected after it has initiated a transaction.
local-bus interface
The local-bus interface is between the PMIF and LBIN modules. The local bus allows access to the EPROM
and the registers on the PHY-layer device. Since several devices are allowed on the local bus, the PCI SAR
accepts a ready signal from devices on the bus as a handshake. This accommodates slow devices such as
EPROMs and is used to relax timing constraints on the register interface for PHY-layer devices. The local bus
is only accessed via PCI-bus transactions with the PCI SAR as the slave (with the exception of the local-bus
interrupt signal). The PCI-bus address must remain stable while the local bus is active.
control-memory interface
The control-memory interface is between the control-memory interface and arbitration (CMIA) and all other
modules that access the control memory. The control memory is set up in a 16K
×
32 configuration with the cycle
time given by the PCI-bus clock. The control-memory interface is designed for an asynchronous SRAM with
a 32-bit data bus, a 14-bit address bus, a read or write signal, and an output-enable (CMOE) signal.
PHY-layer interface
The ATM-cell-transfer rate is full-duplex 149.76 Mbit/s, but data may arrive in bursts at 155.52 Mbit/s due to the
framing scheme described by the PHY layer. A clock rate of at least 19.44 MHz is essential in the receive
direction to prevent cell loss due to buffer overflow in the PHY layer. The PCI SAR decouples the PCI-bus clock
from the PHY-layer clock in the receive direction via an asynchronous FIFO, which holds up to 32 cells. The PCI
SAR transmits data to the PHY layer at the PCI-bus clock rate.
The PCI SAR sends a transmit clock at the PCI clock frequency and a receive clock at 19.44 MHz to the PHY
layer. The transmit clock sent to the PHY layer is an inverted version of the internal clock. This ensures that all
setup- and hold-time restrictions are met. The PCI SAR generates output data along with a start-of-cell indicator
in the transmit direction.
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