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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設裝置帶SBU的主機接口設備） |
| 文件頁數(shù)： | 43/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
43
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
header-type register (offset address 0Eh)
The header-type register is an 8-bit register that describes the format of the PCI configuration-space locations
10h to 3Ch. The header defined here is referred to as type 0. The header-type register is located at offset
address 0Eh in the PCI configuration space and is read only. The current value is 001h.
built-in self-test register (BIST) (offset address 0Fh)
BIST is not supported by the PCI SAR. Reading this register returns 0.
base-address register 0 (offset address 10h)
Power-up software needs to build a consistent address map before booting the machine to the operating
system. This means that questions like how much memory is in the system and how much address space the
I/O controllers in the system require need to be answered. After determining this information, power-up software
can map the I/O controllers into reasonable locations and proceed with the system boot. To do this mapping
in a device independent manner, the base registers for this mapping are placed in a predefined header portion
of configuration space.
The base-address register is updated by the host device during power up. The number of upper bits that a device
implements depends on how much address space is responded to by the device. A device that uses a 64K-byte
address space builds the top 16 bits and hardwires the lower 16 bits. The power-up software determines the
address space required by writing a value of all ones to this register and reading the value back. The device
returns zeros in all do-not-care bits. In the case of TNETA1561, it returns FFFF0000h to specify that it requires
an address space of 64K bytes. The individual bits in the register are described below.
BIT
NAME
DESCRIPTION
RESET
VALUE
0
Memory-space indicator
Bit 0 is used to determine whether the register maps into memory or into I/O space. The
base-address register that maps to memory space must return a 0. The base-address register
that maps to I/O space must return a 1. Since TNETA1561 is a memory-mapped device, bit
0 defaults to 0.
Bits 1–2 have the following encoded meaning:
00 Base register is 32 bits wide and mapping can be done anywhere in the 32-bit
memory space.
01 Base register is 32 bits wide but must be mapped below 1 Mbyte.
10 Base register is 64 bits wide and can be mapped anywhere in the 64-bit address
space.
11 Reserved
Bit 3 is set to 1 if there are no side effects on reads. The device returns all bytes on reads
regardless of the byte enables, and the host bridges can merge processor writes into this range
without causing errors. Bit 3 must be set to 0 for all other conditions.
Bits 4–31 are set by the host device during power up.
0
1–2
Type
00
3
Prefetchable
0
4–31
Base address
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| TNETA1561PGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1570 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE |
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| TNETA1575 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES |
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