參數(shù)資料
型號(hào)： TNETA1561
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 18/49頁(yè)
文件大?。?/td> 976K
代理商： TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
functional overview (see Figure 11) (continued)
The TNETA1561 provides a packet interface that is managed by descriptor rings to make the 53-byte ATM
framing format transparent to the user. The PCI SAR passes the 48-byte payload of each cell across the PCI
bus. All packets are stored in host memory and accessed by PCI SAR by the descriptor-ring mechanism.
The PCI SAR generates data in the transmit direction via a special bit-rate control table that provides explicit
cell-level interleaving between groups of virtual circuits (VCs). This mechanism provides a high degree of
flexibility in specifying peak rates for each group of up to 155 Mbit/s at a resolution greater than 32 kbit/s. The
VCs within a group are serviced via a FIFO discipline on a per-packet basis.
The PCI SAR supports 1023 unique VCs, typically all associated with virtual path identifier (VPI) 0. VPI 0 allows
multiple virtual paths (VPs) with the reminder that each VC is unique. Limited support is provided to recognize
ATM-layer OAM cells. The PCI SAR is primarily intended for ATM AAL5 encapsulation and termination that is
fully supported in hardware. Limited support is provided for AAL3/4 with 48-byte transfers across the PCI-bus
interface and hardware recognition of the EOM indicator on the receive side. In addition, a null AAL is supported
to facilitate real-time data transfer. The interface to the PHY layer consists of an 8-bit-wide datapath and
associated control signals in both the transmit and receive directions. The 53-byte cells pass between the ATM
and PHY layers. The native clock for PCI SAR is the PCI-bus clock frequency of 33 MHz. The 8-bit-wide
datapath on the receive ATM-PHY interface requires a clock rate of at least 19.44 MHz when interacting with
a 155.52-Mbit/s physical layer. The receive interface uses the PHY-layer clock. The native-word size for PCI
SAR is 32 bits, corresponding to the data-bus width for the PCI bus.
functional description
The PCI SAR implements the functions of the transmit and receive modules. The implementation of these
modules is described in terms of their functional blocks. The PCI SAR has the following basic blocks: PCIMAC,
PMIF, LBIN, USR REG, transmit block (XBTP, CA, XALP, XMB FIFO, XPIN), and receive block (RBTP, RALP,
RMB FIFO, RPIN) (see Figure 12).
transmit modules
The transmit host-and-buffer transaction processor (XBTP) is responsible for all host-related functions on the
transmit side. It requests 48-byte transfers from the PCI bus-interface block, PCIMAC. The cell actuator (CA)
accesses the BWG table and determines the next VC to be serviced. The transmit adaptation-layer processor
(XALP) processes all AAL-related functions and adds the four bytes of the ATM header to each cell. The AAL5
cyclic-redundancy check (CRC) is generated by the XBTP module and it is appended to the packet. The transmit
buffer (XMB), a FIFO, is an 8-cell buffer that receives 13 words per cell. Idle cells are also placed in this buffer.
The transmit PHY interface (XPIN) does word-to-byte unpacking and interacts with the PHY layer using the
PCI-bus clock.
receive modules
The receive PHY interface (RPIN) performs byte-to-word packing, filters idle cells, and interacts with the PHY
layer using the system PHY-layer clock crystal. The receive buffer (RMB) performs rate synchronization from
the PHY-layer clock to the PCI-bus clock and buffers up to 32 cells. The receive ATM processor (RAT) and the
receive ATM adaptation-layer processor (RALP) operate in parallel and are part of the same module. The RALP
terminates the AAL5 CRC and processes various EOP indicators. The RAT function is responsible for deleting
the ATM header and accessing the correct receive direct-memory access (DMA) entry. Finally, the receive
host-and-buffer transaction processor (RBTP) performs all host-specific functions on the receive side.
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