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| 型號(hào)： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 19/49頁 |
| 文件大小： | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
PCIMAC
The PCIMAC block is an interface unit between a PCI-based host system and PMIF block of PCI SAR. It masters
the PCI bus in its master mode and allows the host to access the PCI SAR in its slave-mode operation. This
block provides the PCI-bus host interface with all the interface signals for master and slave operations. This
block implements a 32-bit data buffer to provide a datapath to and from the host. This data buffer has an interface
with the XMB FIFO for transmit data and with RMB FIFO for receive data. This module also has a
PCI-configuration space implemented as 32-bit registers.
The PMIF has another interface with PMIF (internal to PCI SAR) that provides all the necessary control signals
enabling PCI SAR to operate in master mode. The operation in slave mode is controlled by the host system.
PMIF
The PMIF block provides interfaces to LBIN, CMIA, XBTP, RBTP, and USR REG blocks. The LBIN function
provides access to the PHY layer and EPROM. The CMIA interface provides a datapath to access control-
memory data. The XBTP and RBTP interfaces provide appropriate signals that make the PCI SAR device a
PCI-bus master for the transmit or receive function.
The USR REG interface provides status and control data for PCI SAR functions. This block also has a SAR
configuration register that is written by the host to enable transmit or receive operation. This block is only a
carrier of data and control signals in either its master- or slave-mode operation. It does not initiate any operation
except generating PCI-bus requests.
CMIA
The CMIA block provides an interface to the control memory using the local memory bus. It performs memory
arbitration for all the functions that access control memory. Each access is a one (32-bit) word access. The
priority mechanism to service various functions is in the following order: RALP, XALP, CA, RBTP, XBTP, and
PMIF.
PHY layer
The PHY-layer interface is serviced by the XPIN and RPIN modules for either reading data from the XMB FIFO
in the transmit direction or writing data to RMB FIFO in the receive direction. Figure 12 depicts the data-flow
representation of the PCI SAR functional block diagram.
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