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參數(shù)資料
| 型號(hào)： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 5/49頁 |
| 文件大小： | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
PHY-layer transmit interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
TCLK
99
O
Transmit clock. The TNETA1561 generates TCLK at the PCI-clock frequency and sends it to the
PHY layer. TCLK is an inverted version of the internal clock.
TDATA7–
TDATA0
97–96,
93–90,
87–86
O
Transmit data. TDATA7–TDATA0 are sent at the rate of the PCI clock and are driven by the
TNETA1561.
TSOC
98
O
Transmit start of cell. TSOC is sent by the PCI SAR to the PHY layer and indicates that the first
byte of an ATM cell was transmitted to the PHY layer.
TXENABLE
102
O
Transmit enable. The SAR turns off TXENABLE when the PHY layer sends the TXFULL signal.
TXFULL
79
I
Transmit buffer full in the PHY layer. The PHY layer asserts TXFULL at least four cycles before
any internal buffers are full. This makes the TNETA1561 stop the data transmission to the PHY
layer.
PCI SAR and control-memory interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
18–17,
15–11,
9–5,
3–2
CMADDR13–
CMADDR0
O
Control-memory address. CMADDR13–CMADDR0 is a 14-bit address bus and is driven by the
PCI SAR.
CMD31–
CMD0
240–239,
236–233,
231–227,
225–221,
219–215,
213–209,
207–203,
201
I/O
Control-memory data. The control-memory interface has a 32-bit data bus. CMD31–CMD0 are
designed for 20-ns asynchronous SRAMs. The TNETA1561 uses this interface to access the
data structures and pointers in the control memory.
CMOE
195
O
Control-memory output enable. CMOE is an active-low signal and is driven by the PCI SAR.
CMR/W
194
O
Control-memory read/write. CMR/W determines a read or write operation. If the output is low,
it is a write operation. If the output is high, it is a read operation. CMR/W is driven by the PCI SAR.
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