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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 32/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
TX descriptor-ring word 3 – AAL5 control/length
AAL5 control field (bits 31 – 16)
AAL5 length field (bits 15 – 0)
The AAL5 control and length fields apply to packets, not to buffers, and this entry is required only in the first
descriptor for the packet. The AAL5 length field is not used to determine the length of the packet during transmit
processing. Both fields are placed in the descriptor ring in an AAL5 packet in the proper position (in the four bytes
preceding the AAL5 32-bit CRC). These fields are not used if the packet is either in AAL3/4 or a null-AAL packet.
transmit BWG DMA block
The control memory on the PCI SAR contains 255 transmit BWG DMA entries, each containing eight words.
The contents of each entry are summarized in the following table.
transmit BWG DMA entry table
ENTRY
DESCRIPTION
STATIC/DYNAMIC
Word 0
Control field, packet length, buffer length
Dynamic
Word 1
Current-buffer pointer – 32 bits
Dynamic
Word 2
4-byte ATM header
Dynamic
Word 3
Static bits – BWG ON/OFF (BWG_ON bit)
Static
Word 4
BWG data-ring pointer, descriptor pointer
Dynamic
Word 5
Reserved
Dynamic
Word 6
Partial 32-bit packet CRC
Dynamic
Word 7
AAL5 tail – control and length fields
Static
The PCI SAR initiates all transactions affecting the DMA table during normal operation based on
cell-transmission opportunities from the BWG table. During initialization, the host has to configure word 0,
word 3, and word 4 (shown in the transmit BWG DMA entry table) for each BWG selected for transmission in
the BWG table including the BWG0. These words allow the TNETA1561 to start a transmission of a new packet.
After configuration, the TNETA1561 reads word 3 to check if the BWG_ON bit is set. If it is set, the device reads
word 0 to determine if the OWN bit is set. When the OWN bit is not set, it indicates that this is the first buffer
of a new packet. The TNETA1561 then reads word 4 to obtain a transmit descriptor-ring pointer that indicates
the memory address in host memory for the transmit descriptor-ring pointer. The following sections explain each
TX DMA table word in detail.
TX DMA word 0 – state/configuration
Control (bits 31 – 27)
Current-packet length (bits 26 –16)
Current-buffer length (bits 15 – 0)
The contents of word 0 are copied directly from the corresponding transmit data-descriptor-ring entry at the start
of each new buffer. This applies to all the fields in this status word, and the host must ensure consistency across
the fields.
OWN (bit 31)
The OWN bit is set when the DMA channel for the BWG is active and all related state information in the DMA
entry is current. The OWN bit indicates a packet is currently being segmented and transmitted for this BWG.
This OWN bit is cleared by the PCI SAR after the entire packet is transmitted, a completion-ring entry is posted,
and an interrupt is generated to the host.
The host sets the OWN bits for individual buffers in a packet in the transmit data-descriptor rings in order from
last to first. This ensures that the DMA block is not held up while waiting to acquire the next buffer from a partially
transmitted packet.
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