參數(shù)資料
型號(hào)： TNETA1561
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 23/49頁(yè)
文件大?。?/td> 976K
代理商： TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
PHY-layer interface (continued)
This data is sent at the rate of the PCI-bus clock. The PHY layer can respond with a full signal, which is asserted
at least four cycles before any internal buffers are full. The PCI SAR then turns off the TXENABLE signal until
the full signal is deasserted. The PHY layer sends a start-of-cell indicator with output data. The empty signal
acts as an inverted enable signal on this interface.
The PHY-layer interrupt signal is directly connected to the PCI-bus interrupt signal; therefore, PCI-bus interrupt
is asserted when the PHY-layer interrupt signal is asserted.
operation
The memory mapping of the PCI SAR local-memory elements is mapped in the host-memory space. The host
memory-block location, which is determined by the host, is not predefined. The host writes the starting address
in the base-address register located in the configuration space. The PCI SAR during read-from or write-to host
memory uses the little-endian addressing scheme. This requires byte swapping of data into big endian and
writing into the XMB FIFO during the transmit operation. The received data bytes from the RMB FIFO must also
be swapped from big endian into little endian.
PCI-bus and data-transfer requirements
The PCI SAR behaves as a PCI-bus DMA master and as a slave. The PCI SAR supports a maximum
AAL5-buffer size of 64K bytes, which corresponds to a maximum AAL5-packet length of 64K bytes. In burst
mode, the data transfer between the PCI SAR and the host is cell based (48 bytes). This transfer is completed
in a single access of the PCI bus, but this is dependent upon the bus latency of the host system. This transfer
is always initiated by the PCI SAR as a master. The data transfer across the PCI bus is word based (4 bytes).
The PCI SAR also supports nonburst transfers as a master and as a slave for host accesses (as defined in the
PCI-bus transaction).
PCI-bus interaction and transfer size
TRANSACTION
PCI SAR ROLE
Slave
Slave
TRANSFER SIZE
Word
Byte/word
One, two, three
or four bytes
Host access – PCI SAR registers, PHY-layer registers and control memory
Host access – PCI-configuration space
Host access – EPROM
Slave
PCI SAR access – Transmit completion ring, transmit descriptor ring,
and receive free-buffer ring transactions
PCI SAR access – Posting to host-receive completion-ring entry
Master
Word
Master
4 Word
1–13 Words
Latency dependent
PCI SAR access – Cell-payload transfers
Master
memory-map table
The following memory-map table defines the offset-address range for the various blocks of the control memory
as they are mapped into host memory. The host-memory base address of the control-memory block is obtained
from the base register 0. This is defined in the paragraph for the PCI SAR configuration-space registers. The
host-memory base address of the EPROM-memory block is obtained from the expansion-ROM base-address
register. These base addresses are defined in the PCI-SAR configuration-space register section.
control-memory block – maximum size of 64K bytes
The first 48K bytes of this block are in the control memory (external to the PCI SAR) and are divided into the
first 16K bytes for the transmit-side information and the next 32K bytes for the receive-side information. The
remaining 16K bytes are divided into 8K bytes each for the USR register (within the PCI SAR) and PHY-layer
register (PHY-layer device external to PCI SAR).
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