參數(shù)資料
型號(hào)： TNETA1561
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁數(shù)： 24/49頁
文件大?。?/td> 976K
代理商： TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
control-memory block – maximum size of 64K bytes (continued)
OFFSET ADDRESS BITS
00000000h – 000003FFh
00000400h – 000023FFh
00002400h – 00003FFFh
00004000h – 0000BFFFh
0000C000h – 0000DFFFh
0000E000h – 0000FFFFh
DESCRIPTION
READ/WRITE REGISTER
R/W
R/W
R/W
R/W
R/W
R/W
Initialization block
Transmit DMA states
BWG table
Receive DMA states
PHY-layer register
USR register
(256 words)
(2K words)
(1.2K words)
(8K words)
(2K words)
(2K words)
indirect local-memory block – maximum size of 8K bytes
The indirect control-memory block includes the following registers for addressing, data, and status information:
REGISTER
SIZE
32 bit
DESCRIPTION
Control-memory address register
Contains the address of the control-memory block
Buffer that provides data read from or written to the control-
memory block
Display PCI SAR register information
Control-memory data register
32 bit
Control-memory control register 1 – register 8
32 bit
EPROM memory block
The TNETA1561 can access an EPROM via the local-bus interface. The maximum-size EPROM that can be
accessed by the TNETA1561 is 8K bytes. There are four sizes of data transfers from the EPROM (one, two,
three, or four byte). To read data from the EPROM, the host generates a 32-bit PCI address and drives the
appropriate byte-enable signals according to the type of transfer being executed.
PHY-layer registers access
The TNETA1561 uses the local-bus interface to access the PHY-layer registers. The host system must use the
PCI interface to address the register in the PHY layer; therefore, a 32-bit address has to be generated from the
host and passed to the TNETA1561. To access a byte-wide address offset for the PHY-layer device registers,
the host software uses the PCI-bus byte-enable signals to specify which data byte to access on the PHY-layer
device. During a write operation to a PHY-layer register, the host uses byte-enable signals to indicate to the
TNETA1561 which data byte contains the valid byte. During a read operation to a PHY-layer register, the
TNETA1561 copies the byte read from the PHY-layer four times to form a 32-bit word. The 32-bit word containing
the PHY-layer data in all four bytes is transferred to the host.
control-memory access
The control memory is accessed by using the offset-address bit of the PCI-bus address. This provides a
14-bit-wide address bus to the control memory. All PCI-bus accesses to control memory are one-word accesses
at word boundaries.
control-memory address map
The data below specifies the PCI SAR slave-mode PCI-bus physical-address ranges for peripheral devices.
MEMORY REGIONS
Initialization block
Transmit BWG 0 – 255 – DMA block
BWG table (1200 words, 4800 entries)
Receive BWG/VCI 0 –1023 – DMA block
CONTROL-MEMORY BASE POINTERS (HEX)
0000h
0100h
0900h
1000h
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