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| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動柜員機(jī)分段和重組的PCI主機(jī)接口（自動柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 41/49頁 |
| 文件大小： | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
41
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
command register (offset address 04h)
The command register provides device control over its ability to generate and respond to PCI cycles. When a
zero is written to this register, the device is logically disconnected from the PCI bus for all accesses except
configuration accesses. On power up and reset, the host places all zeros in this register. However for the normal
operation of the PCI SAR, the host enables the bus master (bit 2) and memory space (bit1) of the command
register. The individual bits in the register and the default values are described below.
BIT
NAME
DESCRIPTION
RESET
VALUE
0
I/O space
Control bit 0 controls the response of the TNETA1561 to I/O space accesses. A value of 0
disables the response of TNETA1561. A value of 1 allows TNETA1561 to respond to I/O space
accesses.
Control bit 1 controls the response of the TNETA1561 to memory space accesses. A value
of 0 disables the response of TNETA1561. A value of 1 allows TNETA1561 to respond to
memory space accesses.
Control bit 2 controls the ability of the TNETA1561 to act as a master on the PCI bus. A value
of 0 disables TNETA1561 from generating PCI accesses. A value of 1 allows TNETA1561 to
act as a bus master.
Control bit 3 controls the action of the TNETA1561 on special cycle operation. A value of 0
causes TNETA1561 to ignore all special cycle operations. A value of 1 allows the TNETA1561
to monitor special cycle operations.
Control bit 4 is an enable bit for using memory write and invalidate command. When this bit
is 1, the master can generate the command. When the bit is 0, memory write must be used
instead.
Control bit 5 controls how VGA-compatible and graphics devices handle accesses to
VGA-palette registers.
Control bit 6 controls the response of the TNETA1561 to parity errors when the bit is set. The
device must take its normal action when a parity error is detected. When the bit is 0, the device
must ignore any parity errors that it detects and continue normal operation.
Control bit 7 controls whether or not a device does address data stepping.
0
1
Memory space
0
2
Bus master
0
3
Special cycles
0
4
Memory write and
invalidate enable
0
5
VGA palette snoop
0
6
Parity error response
0
7
Wait cycle control
0
8
PSERR enable
Control bit 8 is an enable bit for the PSERR driver. A value of 0 disables PSERR driver. After
PRST, control bit 8 goes to 0.
Control bit 9 controls whether or not a master can do back-to-back transactions to different
devices. Initialization software sets the bits if all targets are fast back-to-back capable.
Reserved
0
9
Fast back-to-back enable
0
10–15
Reserved
0
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