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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設裝置帶SBU的主機接口設備） |
| 文件頁數(shù)： | 30/49頁 |
| 文件大小： | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit descriptor-ring summary
The data below shows the composition of the four-word entry.
ENTRY
DESCRIPTION
Word 0
Control field, packet length, buffer length
Word 1
Start-of-buffer pointer – 32 bits
Word 2
4-byte ATM header
Word 3
AAL5 tail – control and length fields
TX descriptor-ring word 0 – configuration
Control (bits 31 – 27)
Current-packet length (bits 26 –16)
Current-buffer length (bits 15 – 0)
OWN (bit 31)
The descriptor is owned by the PCI SAR when the OWN bit is set. The descriptor is owned by the host when
the OWN bit is zero. The OWN bit is set by the host when a buffer/packet is queued for transmission. When the
next BWG index from the BWG table does not have an active buffer location in the transmit DMA entry, the
PCI SAR attempts to recover a new-buffer-descriptor entry from the transmit data-descriptor ring. This entry
is loaded into the DMA entry if the OWN bit is set. If the OWN bit for the first descriptor in the transmit
data-descriptor ring is zero, no data is queued for transmission and an idle cell is transmitted.
The host places all the buffers for a packet in the descriptor ring before setting the OWN bits on the entries
representing each buffer in sequence from the last buffer to the first buffer (in reverse order). The PCI SAR clears
the OWN bit after it finishes transmitting/processing the bytes associated with the buffer that is pointed to by
the DMA entry. When the OWN bit is cleared by the host, word 0 is not meaningful and is overwritten by the host.
start of chain (SOC) (bit 30)
The SOC bit indicates that this is the first buffer of a packet, which consists of one or more buffers. This bit is
also set in packets with single buffers.
end of chain (EOC) (bit 29)
The EOC bit indicates that this is the last buffer of a packet. Single buffer packets have both the SOC and EOC
bits set. Packets with multiple buffers have the SOC bit set on the first buffer and the EOC bit set on the last
buffer.
interrupt-control bit (ICB) (bit 28)
The ICB bit controls interrupt posting by the PCI SAR to the host after a packet has been transmitted. The setting
of ICB to active high disables posting of interrupts to the host by the PCI SAR after a posting of a packet
completion is done for this transmit descriptor ring.
AAL-type – AAL5 indicator (bit 27)
The AAL-type bit indicates that the packet/buffer described in this descriptor-ring entry is an AAL5 packet. When
zero, this bit indicates to the PCI SAR that AAL5 processing is being performed in the transmit direction. This
includes addition of the pad, the control- and packet-length fields, and the 32-bit CRC. The total size of the AAL5
packet is a multiple of 48 bytes. The PCI SAR implements the functions related to packet length and the
generation of the pad. The PCI SAR does not perform any packet-level encapsulation similar to that used in
AAL5 for either AAL3/4 or the null AAL. The host provides packets correctly formatted into 48-byte cells to the
PCI SAR.
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