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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設裝置帶SBU的主機接口設備） |
| 文件頁數(shù)： | 44/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
44
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
expansion-ROM base-address register (offset address 30h)
Some PCI devices, especially those that are defined for use on add-in modules in PC architectures, require local
EPROMs for expansion ROM. The base address and the size information of the expansion ROM is handled
by the expansion-ROM base-address register.
On power up and reset, the bits of this register are set to 0. However, if the host needs to access the EPROM,
bit 0 is set to 1. The individual bits in the register are described below.
BIT
NAME
DESCRIPTION
RESET
VALUE
0
Address-decode
enable
Bit 0 is used to control whether or not the device accepts accesses to its expansion ROM. When
this bit is 0, the devices expansion-ROM address space is disabled. When this bit is 1, address
decoding is enabled using the parameters in the other part of the register. This allows the device
to be used with or without an expansion ROM depending on the system configuration.
The memory-space bit in the command register has precedence over this bit. A device must
respond to accesses to expansion ROM only when the memory-space bit is set and the
expansion-ROM base-address enable bit are set.
After RST, the value in bit 0 goes to 0.
Reserved
Bits 11–31 correspond to the upper 21 bits of the expansion-ROM base address. However, only
the top 16 bits are used since the expansion ROM needs only 64K bytes.
0
1–10
Reserved
Expansion-ROM
base address
11–31
interrupt-line register (offset address 3Ch)
The interrupt-line register is an 8-bit register that is used to communicate the routing of the interrupt. This register
is written by the HOST software during system initialization. The value in this 8-bit register indicates which input
of the system-interrupt controller is connected to the PCI-SAR interrupt terminal. The typical value is between
0 and 15. The interrupt-line register is located at offset address 3Ch in the PCI configuration space and is read
and written by the host.
interrupt-pin register (offset address 3Dh)
The interrupt-pin register is an 8-bit register indicating the interrupt pin that the TNETA1561 is using. The PCI
SAR is defined as a single-function device, uses only interrupt A, and has a value of 1. The interrupt-pin register
is located at offset address 3Dh in the PCI configuration space and is read only.
minimum-grant register (offset address 3Eh)
The minimum-grant register is an 8-bit register that specifies the length of the data burst required by the
TNETA1561 for every PCI-bus grant. This specifies the length of the burst period that the PCI-SAR device needs
in 0.25-
μ
s units. The typical value of 0.75
μ
s (decimal 3) is defined for PCI SAR. The minimum-grant register
is located at offset address 3Eh in the PCI configuration space and is read only.
maximum-latency register (offset address 3Fh)
The maximum-latency register is an 8-bit register that defines the maximum-latency value for the PCI SAR. This
specifies how often the PCI-SAR gains access to PCI bus in 0.25-
μ
s units. A typical value of 10
μ
s (decimal 40)
is defined for PCI SAR. The maximum-latency register is located at offset address 3Fh in the PCI configuration
space and is read only.
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