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參數(shù)資料
| 型號(hào)： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 42/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
status register (offset address 06h)
The status register is a 16-bit register that contains status information for the PCI-bus related events. The status
register is located at offset address 06h in the PCI configuration space. Reads to this register behave normally.
Writes are slightly different in that bits can be reset but not set. A bit is reset when the register is written and the
data in the corresponding location is a one. For example, to clear bit 14 and not affect any other bits, write the
value 0100_0000_0000_0000b. On power up and reset, this register is set to 0000001000000000. This register
is set by the host and is not programmable. The individual bits in the status register are described in the following
table.
BIT
NAME
DESCRIPTION
RESET
VALUE
0
0–6
Reserved
Fast back-to-back
enable
Status bits 0–6 always return to 0.
7
Status bit 7 indicates that the device is capable of performing fast back-to-back transitions.
0
8
Data parity reported
Status bit 8 is set only by master devices. It is set when three conditions are met:
1. The bus agent asserted PERR itself or observed PERR asserted.
2. The agent setting the bit acted as the bus master for the operation in which the error
occurred.
3. The parity error response in the command register is set.
0
9–10
PDEVSEL timing
Status bits 9–10 encode the timing of PDEVSEL. There are three allowable timings for
PDEVSEL. They are 00b for fast, 01b for medium, and 10b for slow.
Status bit 11 is set by the target device when it terminates a transaction with target abort.
Status bit 12 is set by the master device when its transaction is terminated with target abort.
Status bit 13 must be set by a master device when its transaction is terminated with master
abort.
01
11
12
Signaled target abort
Received target abort
0
0
13
Initiated master abort
0
14
Signaled-system error
Status bit 14 must be set when the system asserts PSERR.
Status bit 15 is set by the device when it detects a parity error even if the parity handling is
disabled by the parity-error response bit in the command register.
0
15
Detected-parity error
0
revision-ID register (offset address 08h)
The revision-ID register is an 8-bit register that specifies a device-specific revision-identifier number. The
current value of the register is 00h. The revision ID register is located at offset address 08h in the PCI
configuration space and is read only.
class-code register (offset address 09h)
The class-code register is a 24-bit register that specifies the generic function of the device. The class code
register is located at offset address 09h in the PCI configuration space and is read only. The current value is
028000h for a network controller.
cache line-size register (offset address 0Ch)
The PCIMAC supports write and invalidate as a master. The host writes the cache line size into this byte-wide
register.
latency-timer register (offset address 0Dh)
The latency-timer register is an 8-bit register that specifies the maximum time TNETA1561 device can continue
with bus-master transfers. The PCIMAC supports a burst of more than one data cycle. The host sets the latency
requirements of the system in this register in PCI-bus clock units. When the current-time value (00h) stored in
the latency-timer register expires, the TNETA1561 immediately releases the bus after finishing the current data
phase.
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