參數(shù)資料
型號(hào)： TNETA1561
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 47/49頁(yè)
文件大小： 976K
代理商： TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
47
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
enable-transmit operation (EN transmit) (bit 1)
The EN-transmit bit allows the host to disable packet-to-cell segmentation and any payload-data transfer from
the host to the link. The EN-transmit bit is set high to enable normal transmit processing and set to zero to disable
such processing. The EN-transmit bit is set to zero on reset, disabling transmit operation until various
configuration registers, the BWG table, and DMA blocks are configured by the host. The transfer of the new cells
from PCI bus to PCI SAR is inhibited when the enable-transmit bit is disabled. Cells already in the output buffer
are forwarded to the PHY layer.
enable-receive operation (EN receive) (bit 2)
The EN-receive bit allows the host to disable packet reassembly. All cells from the PHY layer are dropped when
the EN-receive bit is zero. The EN-receive bit is set high to enable normal processing and is set to zero on reset,
disabling receive operation until various configuration registers and the DMA blocks are reconfigured by the
host. The transfer of the new cells from ATM link to the receive buffer is inhibited when the enable-receive bit
is disabled.
SDH bit (bit 5)
If the SDH bit is set to zero, the TNETA1561 transmits null cells (unassigned cells) when no valid cells are ready
for transmission. If SDH bit is set to one, the device transmits idle cells as fillers.
BWG table-size register (offset address 00E014h)
Unused (bits 31–11)
BWG table size (bits 10–0)
The 11-bit BWG table-size register allows the user to configure the size of the BWG table in 4-byte words. Each
word in the table consists of four 8-bit entries. The maximum table size is 1200 (decimal) allowing 4800 entries.
A resolution of 32 kbit/s is achieved with 4800 entries. The number of entries in the table is one more than the
number programmed in this register and there is one entry in the table when the register is set to zero.
transmit/receive FIFO maximum-depth register (offset address 00E018h)
Unused (bits 31–20)
Maximum receive FIFO depth (bits 19–10)
Maximum transmit FIFO depth (bits 9–0)
This is the only set of statistics collected by the TNETA1561 because it is useful information for queuing analysis
in different platforms with varying PCI-bus clock speeds and latencies. These registers are not of the read and
reset variety and must be set to zero to restart the measurement.
Clear transmit-freeze command (offset address 00E020h)
The transmit-freeze bit is set when the transmit completion-ring not-available bit is set and the transmit side is
disabled. The host enables the transmit side by writing any value into this register.
Clear receive-freeze command (offset address 00E024h)
The receive-freeze bit is set when the receive completion-ring not-available bit is set and the receive side is
disabled. The host enables the receive side by writing any value into this register.
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