參數(shù)資料
型號(hào)： TNETA1561
廠商： Texas Instruments, Inc.
英文描述： ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口)
中文描述： 自動(dòng)柜員機(jī)分段和重組的PCI主機(jī)接口（自動(dòng)柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備）
文件頁(yè)數(shù)： 14/49頁(yè)
文件大?。?/td> 976K
代理商： TNETA1561
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics (see Note 6 and Figure 7)
NO.
MIN
TYP
30
MAX
UNIT
1
td(LBPHYCS)1
Delay time, LBRD
↓
to LBPHYCS
↓
ns
2
td(LBPHYCS)2
Delay time, LBREADY
↓
to LBPHYCS
↑
95
ns
These values are given for operation with a 33-MHz PCI clock.
NOTE 6: If LBREADY does not go active low within eight PCI clocks after LBPHYCS goes active low, the TNETA1561 latches in the data of the
LBD7–LBD0 bus and terminates the read operation.
LBRW
(output)
LBRD
(output)
LBADDR15–
LBADDR0
(output)
LBD7–
LBD0
(input)
LBREADY
(input)
LBPHYCS
(output)
1
2
Figure 7. Local-Bus-Interface Read Operation (TNETA1561 as Slave)
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