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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 38/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
end-of-packet wait (bit 24)
This bit must be set to zero by the device driver during initialization. This gives the SAR the responsibility of
setting it to one in DMA word 0 (when this feature is enabled). This bit is a status bit used by the TNETA1561
during operation.
enable end-of-packet wait (bit 23)
When a start of a packet is detected by the TNETA1561, the TNETA1561 requests a buffer from the host
memory. If the buffer is not available, the first cell of this packet is dropped. The rest of the packet is dropped
after it is received. The host can set bit 23 to one to enable the TNETA1561 to drop the cells of a packet that
had the first cell dropped. Once the TNETA1561 detects the end packet, it begins to receive packets in this VCI.
This feature only works for AAL5 and ALL3/4. For null-AAL and OAM cells, bit 23 must be set to zero.
EFCN cell-counter place holder (bits 21–11)
This field is set to zero since it is a place holder for the EFCN cell counter in word 0 of this DMA block.
AAL-packet length (bits 10–0)
The AAL-packet-length field in word 3 indicates the length of the buffer in cells for each packet in this BWG. This
is used in different ways based on whether the BWG supports AAL5 or AAL3/4 packets or null-AAL packets.
This field indicates the length of the buffer size allocated by entries in the free-buffer ring used by this BWG for
AAL5 or AAL3/4 packets. This is used to detect buffer overflow.
When the null-AAL indicator is set, this field programmed in two’s-complement notation represents the number
of cells in each null-AL packet. Since receive DMA channel 0 operates off the null-AAL mode with each packet
size equal to one cell, this field is programmed with the value of one in two’s-complement notation (7FFhex).
RX DMA word 5 – AAL5 partial CRC
Partial AAL5 receive CRC (bits 31–0)
This field stores the 32-bit CRC that is calculated over the entire payload of each received AAL5 packet. The
CRC is stored in the last four bytes of the last cell in the AAL5 frame. The CRC check results in a unique
polynomial.
receive completion ring
The following table shows the composition of a 4-word receive-completion-ring entry. The receive completion
ring has 256 entries. The PCI SAR posts an item to the next entry in the completion ring when it completes
reassembly on a packet. The receive-completion-ring pointer maintains the value of the current entry within the
PCI SAR. The host can recalibrate to this by reading the value from the initialization section in control memory.
receive-completion-ring summary
ENTRY
DESCRIPTION
Word 0
Reserved
Word 1
Start-of-buffer pointer – 28 bits
Word 2
4-byte ATM header
Word 3
Control field, EFCN cells received, packet length
RX completion-ring word 0 – reserved
This word is not used or defined.
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| TNETA1561PGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1570 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE |
| TNETA1570MFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Segmentation and Reassembly Circuit |
| TNETA1570PGW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1575 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES |
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