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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 36/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receive DMA-virtual-channel entry summary
ENTRY
DESCRIPTION
STATIC/
DYNAMIC
Word 0
Control, status, EFCN cell count, current packet length
Dynamic
Word 1
Current-buffer pointer – 28 bits
Dynamic
Word 2
Start-of-buffer pointer – 28 bits
Static
Word 3
Control, packet length
Static
Word 4
Reserved
Word 5
AAL5 partial CRC – 32 bits
Dynamic
Word 6
Reserved
Word 7
Reserved
RX DMA word 0 – VC status/configuration
Control (bits 31–23)
Unused (bit 22)
Current-congestion number (bits 21–11)
Current-packet length (bits 10–0)
OWN (bit 31)
The OWN bit is set when the DMA channel for this BWG is active and all DMA parameters such as the
receive-data pointer, buffer length, and packet length are current. The OWN bit is set by the PCI SAR when
word 3 is copied to word 0 at the start of each new packet. The bit is cleared by the PCI SAR when the entire
packet has been posted to a buffer in host memory. The BWG is inactive when the OWN bit is zero. Then, the
free-buffer ring indicated in word 3 is used to poll a new buffer on the arrival of the first cell of a new packet on
the VCI used to index this BWG.
static-configuration bits from word 3
The next summary lists five static-configuration bits copied from word 3 at the start of each packet. Each is
described in detail in the section on RX DMA word 3.
RX DMA word 0 static-configuration bit summary
LOCATION
FIELD
Bit 31
OWN
Bit 30
VCON
Bit 29
Buffer type: small or big
Bit 28
Null-AAL indication
Bit 25
AAL3/4 indication
Bit 24
End-of-packet wait
Bit 23
Enable end-of-packet wait
explicit-forward congestion-notification (EFCN) cell counter (bits 21–11)
The number of cells received with the EFCN indicator set in each packet is counted and the value is stored in
this field. The EFCN indication is given a logic value of 01x in the PTI field of the ATM header. This value is
passed to the receive completion ring at the end of each packet. Since this field is copied from word 3 at the
start of each new packet, it is reset to zero at this time.
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