- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385942 > TNETA1561 (Texas Instruments, Inc.) ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) PDF資料下載
參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機(jī)接口) |
| 中文描述： | 自動柜員機(jī)分段和重組的PCI主機(jī)接口（自動柜員機(jī)分段和重設(shè)裝置帶SBU的主機(jī)接口設(shè)備） |
| 文件頁數(shù)： | 35/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
TX completion-ring word 0
OWN (bit 31)
This completion-ring entry is owned by the PCI SAR when the OWN bit is set. The completion-ring entry is
owned by the host when the OWN bit is zero. The PCI SAR uses the next completion-ring entry in the ring if
the OWN bit is set. The TNETA1561 clears the OWN bit after updating the entry. The host then receives an
interrupt and retrieves the next entry in the completion ring to post the completion of packet transmission for
a BWG and the release of the buffer space occupied by the buffers constituting the packet. The host then sets
the OWN bit to allow the PCI SAR to use the completion-ring entry when it has queued a packet for transmission.
If the OWN bit is not set when the PCI SAR is ready to post a completed packet, a status bit is set in the
hardware-status register and an interrupt is generated if the error condition is unmasked.
BWG index (bits 7–0)
The only item that is posted to the transmit completion ring when the PCI SAR completes transmission of a
packet is the BWG index. This is adequate for the host to locate the transmit-buffer pointers to the buffer
locations where data for the packet was stored and reclaim the buffer space.
receive free-buffer-ring format
There are two free-buffer rings. A receive free-buffer-ring entry consists of one word. Each of the two rings has
256 entries. The host places free-buffer pointers in the entries of each ring. The PCI SAR removes a pointer
when it starts processing each new packet from the link.
receive free-buffer-ring summary
ENTRY
DESCRIPTION
Word 0
OWN (bit 31)
Unused (bits 30–28)
Start-of-buffer pointer (bits 27–0)
RX free-buffer-ring word 0
OWN (bit 31)
Each free-buffer-ring entry is owned by the PCI SAR when the OWN bit is set and it is owned by the host when
the OWN bit is zero. The host sets the OWN bit for new entries placed in the free-buffer rings. The PCI SAR
uses the next free-buffer-ring entry in the respective ring if the OWN bit is set. The PCI SAR clears the OWN
bit after acquiring the buffer and releasing the ring location to the host. The buffer is not freed until a packet is
posted to the receive completion ring. If the OWN bit is not set when the PCI SAR polls a free-buffer ring for a
new entry, a status bit is set in the hardware-status register and an interrupt to host is generated if the error
condition is unmasked.
start-of-buffer pointer (bits 27–0)
A pointer to a buffer, aligned to a 16-byte boundary, is the only information placed in each free-buffer ring.
receive DMA block
The PCI SAR supports 1024 receive DMA-channel entries with each containing eight words. Each DMA channel
represents a VCI on which data is received, and DMA entries in the control memory are indexed by incoming
VCIs. The PCI SAR initiates all transactions affecting the DMA table, except those required for one-time
configuration of a channel in word 3, during normal operation based on the header of cells received from the link.
Data with the PTI field equal to 10X, representing VC-level OAM cells, is diverted to DMA channel 0 that
operates in the null-AAL mode with a packet length of one cell. Word 0 in each receive DMA-channel entry is
copied from word 3 at the start of each new packet. A number of the fields in word 0 represent the dynamic state
of the reassembly process for a cell. The fields in word 3 represent one-time configuration values for the VC
entered by the host. PCI SAR accesses word 0 during normal cell-level processing to retrieve configuration
items.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TNETA1600 | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時(shí)鐘發(fā)生裝置) |
| TO-252 | TO-252 (MP-3Z) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TNETA1561PGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1570 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE |
| TNETA1570MFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Segmentation and Reassembly Circuit |
| TNETA1570PGW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1575 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。