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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 40/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
40
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
TNETA1561 configuration-space registers
The TNETA1561 supports the 64-byte header that is defined by the PCI specification revision 2.0. None of the
device-specific registers in locations 64–255 are used. The predefined header region has a size of 64 bytes.
The layout of the PCI configuration-space registers is shown below.
ADDRESS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
READ/WRITE
0x00
Device ID
Vendor ID
R
0x04
Status
Command
R/W
0x08
Class code
Revision ID
Cache line size
R
0x0C
BIST
Header type
Latency timer
R/W
0x10
Base address 0
Base address 1
Base address 2
Base address 3
Base address 4
Base address 5
R/W
0x14
R/W
0x18
R/W
0x1C
R/W
0x20
R/W
0x24
R/W
0x28
Reserved (returns 0 when read)
0x2C
Reserved (returns 0 when read)
0x30
Expansion ROM base address
R/W
0x34
Reserved (returns 0 when read)
0x38
Reserved (returns 0 when read)
0x3C
Maximum latency
Minimum grant
Interrupt pin
Interrupt line
R/W
0x40
Reserved (returns 0 when read)
0x44–0xFF
Registers not implemented and return 0
Reserved (returns 0 when read)
R
The PCI configuration-space registers are accessible only by PCI-configuration cycles. All multibyte numeric
fields follow little-endian byte format.
vendor-ID register (offset address 00h)
The vendor-ID register is a 16-bit register that identifies the manufacturer of the TNETA1561. The Texas
Instruments (TI) vendor ID is 104Ch. The vendor ID is assigned by the PCI special-interest group. The vendor-ID
register is located at offset address 00h in the PCI configuration space and is read only.
device-ID register (offset address 02h)
The device-ID register is a 16-bit register that uniquely identifies the TNETA1561 device within TI’s product line.
The device ID assigned by TI is A100h. The device-ID register is located at offset address 02h in the PCI
configuration space and is read only.
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