
March 22, 2006 S29NS-J_00_A10
S29NS-J
57
D a t a S h e e t
AC Characteristics
Notes:
1.
Figure shows total number of clock cycles set to four.
2.
If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and are indicated by RDY.
Figure 12. Burst Mode Read (40 MHz)
Da
Da + 1
Da + 2
Da + n
OE#
A/DQ15
–
A/DQ0
Amax
–
A16
Aa
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVDS
t
AVDH
t
AVDO
t
ACH
t
BACC
t
OE
t
OEZ
t
CEZ
t
IACC
t
BDH
Aa
4 cycles for initial access shown.
Programmable wait state function is set to 02h.
25 ns typ.
t
RACC
Hi-Z
Hi-Z
Hi-Z
t
RYDS