參數(shù)資料
型號(hào)： S29NS032JPLBFW002
廠商： Spansion Inc.
英文描述： 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
中文描述： 110納米CMOS 1.8伏只有同時(shí)讀/寫(xiě)，突發(fā)模式閃存
文件頁(yè)數(shù)： 38/85頁(yè)
文件大?。?/td> 799K
代理商： S29NS032JPLBFW002
34
S29NS-J
S29NS-J_00_A10 March 22, 2006
D a t a S h e e t
The system
must
issue the reset command to return a bank to the read (or erase-suspend-read)
mode if DQ5 goes high during an active program or erase operation, or if the bank is in the au-
toselect mode. See the next section,
Reset Command
, for more information.
See also
Requirements for Asynchronous Read Operation (Non-Burst)
and
Requirements for Syn-
chronous (Burst) Read Operation
in the
Device Bus Operations
section for more information. The
Asynchronous Read
and
Synchronous/Burst Read
tables provide the read parameters, and Fig-
ures
11
and
13
show the timings.
Set Configuration Register Command Sequence
The configuration register command sequence instructs the device to set a particular number of
clock cycles for the initial access in burst mode. The number of wait states that should be pro-
grammed into the device is directly related to the clock frequency. The first two cycles of the
command sequence are for unlock purposes. On the third cycle, the system should write C0h to
the address associated with the intended wait state setting (see
Table 11
). Address bits A17–A12
determine the setting. Note that addresses A
max
–A18 are shown as “0” but are actually don’t
care.
Table 11. Burst Modes
Note:
The burst mode is set in the third cycle of the Set Wait State command sequence.
Upon power up, the device defaults to the maximum seven cycle wait state setting. It is recom-
mended that the wait state command sequence be written, even if the default wait state value is
desired, to ensure the device is set as expected. A hardware reset will set the wait state to the
default setting.
Handshaking Feature
The host system should set address bits A17–A12 to “000011” for a clock frequency of 54 or 66
MHz, assuming continuous burst is desired in both cases, for optimal burst operation.
Table 12
describes the typical number of clock cycles (wait states) for various conditions.
Burst
Mode
Third Cycle Addresses for Wait States
W ait States
0
1
2
3
4
5
Clock Cycles
2
3
4
5
6
7
Continuous
00555h
01555h
02555h
03555h
04555h
05555h
8-word Linear (wrap around)
08555h
09555h
0A555h
0B555h
0C555h
0D555h
16-word Linear (wrap around)
10555h
11555h
12555h
13555h
14555h
15555h
32-word Linear (wrap around)
18555h
19555h
1A555h
1B555h
1C555h
1D555h
8-word Linear (no wrap
around)
28555h
29555h
2A555h
2B555h
2C555h
2D555h
16-word Linear (no wrap
around)
30555h
31555h
32555h
33555h
34555h
35555h
32-word Linear (no wrap
around)
38555h
39555h
3A555h
3B555h
3C555h
3D555h
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參數(shù)描述
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