參數(shù)資料
型號(hào)： S29NS032JPLBFW002
廠商： Spansion Inc.
英文描述： 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
中文描述： 110納米CMOS 1.8伏只有同時(shí)讀/寫(xiě)，突發(fā)模式閃存
文件頁(yè)數(shù)： 19/85頁(yè)
文件大?。?/td> 799K
代理商： S29NS032JPLBFW002
March 22, 2006 S29NS-J_00_A10
S29NS-J
15
D a t a S h e e t
Continuous Burst
When the device first powers up, it is enabled for asynchronous read operation. The device will
automatically be enabled for burst mode and addresses will be latched on the first rising edge on
the CLK input, while AVD# is held low for one clock cycle. Prior to activating the clock signal, the
system should determine how many wait states are desired for the initial word (t
IACC
) of each
burst session. The system would then write the Set Configuration Register command sequence.
The initial word is output t
IACC
after the rising edge of the first CLK cycle. Subsequent words are
output t
BACC
after the rising edge of each successive clock cycle, which automatically increments
the internal address counter.
Note that the device has a fixed internal address boundary
that occurs every 64 w ords, starting at address 00003Fh. The transition from the high-
est address to 000000h is also a boundary crossing
. During a boundary crossing, there is a
two-cycle latency between the valid read at address 00003Eh and the valid read at address
00003Fh (or between addresses offset from these values by the same multiple of 64 words). RDY
is deasserted during the two-cycle latency, and it is reasserted in the third cycle to indicate that
the data at address 00003Fh (or offset from 3Fh by a multiple of 64 words) is ready. See
Figure
21
.
The device will continue to output continuous, sequential burst data, wrapping around to address
000000h after it reaches the highest addressable memory location, until the system asserts CE#
high, RESET# low, or AVD# low in conjunction with a new address. See
Table 1
. The reset com-
mand does
not
terminate the burst read operation.
If the host system crosses the bank boundary while reading in burst mode, and the device is not
programming or erasing, a two-cycle latency will occur as described above. If the host system
crosses the bank boundary while the device is programming or erasing, the device will provide
asynchronous read status information. The clock will be ignored. After the host has completed
status reads, or the device has completed the program or erase operation, the host can restart a
burst operation using a new address and AVD# pulse.
If the clock frequency is less than 6 MHz during a burst mode operation, additional latencies will
occur. RDY indicates the length of the latency by pulsing low.
8-, 16-, and 32-W ord Linear Burst w ith W rap Around
These three modes are of the linear wrap around design, in which a fixed number of words are
read from consecutive addresses. In each of these modes, the burst addresses read are deter-
mined by the group within which the starting address falls. The groups are sized according to the
number of words read in a single burst sequence for a given mode (see
Table 2
.)
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS032JPLBFW003 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032JPLBJW000 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032JPLBJW002 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032JPLBJW003 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS064J0LBAW00 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
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