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S29NS-J
S29NS-J_00_A10 March 22, 2006
D a t a S h e e t
As an example: if the starting address in the 8-word mode is 39h, the address range to be read
would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h. The burst se-
quence begins with the starting address written to the device, but wraps back to the first address
in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin
their burst sequence on the starting address written to the device, and then wrap back to the first
address in the selected address group.
Note that in these three burst read modes the ad-
dress pointer does not cross the boundary that occurs every 64 w ords; thus, no w ait
states are inserted ( except during the initial access) .
8-, 16-, and 32-W ord Linear Burst w ithout W rap Around
In these modes, a fixed number of words (predefined as 8,16,or 32 words) are read from con-
secutive addresses starting with the initial word, which is written to the device. When the number
of words has been read completely, the burst read operation stops and the RDY output goes low.
There is no group limitation and is different from the Linear Burst with Wrap Around.
See
Table 11
and
Table 18
for the command of setting the 8-, 16-, and 32- Word Burst without
Wrap Around.
As an example, for 8-word length Burst Read, if the starting address written to the device is 39h,
the burst sequence would be 39-3A-3B-3C-3D-3E-3F-40h, and the read operation will be termi-
nated at 40h. In a similar fashion, the 16-word and 32-word modes begin their burst sequence
on the starting address written to the device, and Continuously Read to the predefined word
length, 16 or 32 words.
The operation is similar to the Continuous Burst, but will stop the operation at fixed word length.
It is possible the device crosses the fixed internal address boundary that occurs every 64 words
during burst read; a latency occurs before data appears for the next address and RDY is pulsing
low. If the host system crosses the bank boundary, the device will react in the same manner as
in the Continuous Burst.
If the clock frequency is less than 6 MHz during a burst mode operation, additional latencies will
occur. RDY indicates the length of the latency by pulsing low.
Programmable Wait State
The programmable wait state feature indicates to the device the number of additional clock cycles
that must elapse after AVD# is driven active before data will be available. Upon power up, the
device defaults to the maximum of seven total cycles. The total number of wait states is program-
mable from two to seven cycles.
The wait state command sequence requires three cycles; after the two unlock cycles, the third
cycle address should be written according to the desired wait state as shown in
Table 11
. Address
bits A11-A0 should be set to 555h, while addresses bits A17-A12 set the wait state. For further
details, see
“Set Configuration Register Command Sequence”
.
Table 2. Burst Address Groups
Mode
Group Size
Group Address Ranges
8-word
8 words
0-7h, 8-Fh, 10-17h, 18-1Fh...
16-word
16 words
0-Fh, 10-1Fh, 20-2Fh, 30-3Fh...
32-word
32 words
00-1Fh, 20-3Fh, 40-5Fh, 60-7Fh...