參數(shù)資料
型號: S29GL128N10TAIV13
廠商: SPANSION LLC
元件分類: PROM
英文描述: 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology
中文描述: 8M X 16 FLASH 3V PROM, 100 ns, PDSO56
封裝: MO-142BEC, TSOP-56
文件頁數(shù): 89/100頁
文件大?。?/td> 952K
代理商: S29GL128N10TAIV13
S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit Flash Family
87
D a t a S h e e t
Erase And Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V
CC
, 10,000 cycles, checkerboard
pattern.
2. Under worst case conditions of 90°C, V
CC
= 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
words program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See
Table 12 on page 63
and
Table 14 on page 65
for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
Parameter
Typ
(Note 1)
Max
(Note 2)
Unit
Comments
Sector Erase Time
0.5
3.5
sec
Excludes 00h
programming prior to
erasure
(Note 5)
Chip Erase Time
S29GL128N
64
256
sec
S29GL256N
128
512
S29GL512N
256
1024
Total Write Buffer
Programming Time
(Note 3)
240
μs
Excludes system level
overhead
(Note 6)
Total Accelerated Effective
Write Buffer Programming
Time
(Note 3)
200
μs
Chip Program Time
(Note 4)
S29GL128N
123
sec
S29GL256N
246
S29GL512N
492
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
TSOP
6
7.5
pF
BGA
4.2
5.0
pF
C
OUT
Output Capacitance
V
OUT
= 0
TSOP
8.5
12
pF
BGA
5.4
6.5
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
TSOP
7.5
9
pF
BGA
3.9
4.7
pF
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