參數(shù)資料
型號： S29GL128N10TAIV13
廠商： SPANSION LLC
元件分類： PROM
英文描述： 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology
中文描述： 8M X 16 FLASH 3V PROM, 100 ns, PDSO56
封裝： MO-142BEC, TSOP-56
文件頁數(shù)： 7/100頁
文件大?。?/td> 952K
代理商： S29GL128N10TAIV13
October 13, 2006 S29GL-N_00B3
S29GL-N MirrorBit Flash Family
5
D a t a S h e e t
Read-Only Operations ......................................................................................77
Figure 11. Read Operation Timings....................................... 78
Figure 12. Page Read Timings.............................................. 78
Hardware Reset (RESET#) ...............................................................................79
Figure 13. Reset Timings..................................................... 79
Erase and Program Operations .....................................................................80
Figure 14. Program Operation Timings .................................. 81
Figure 15. Accelerated Program Timing Diagram .................... 81
Figure 16. Chip/Sector Erase Operation Timings..................... 82
Figure 17. Data# Polling Timings
(During Embedded Algorithms) ............................................ 83
Figure 18. Toggle Bit Timings (During Embedded Algorithms) .. 84
Figure 19. DQ2 vs. DQ6 ...................................................... 84
Alternate CE# Controlled Erase and Program Operations-
S29GL128N, S29GL256N, S29GL512N .........................................................85
Figure 20. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.............................................................. 86
Erase And Programming Performance . . . . . . . . 87
TSOP Pin and BGA Package Capacitance . . . . . 87
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 88
TS056—56-Pin Standard Thin Small Outline Package (TSOP) .............88
LAA064—64-Ball Fortified Ball Grid Array (FBGA) ...............................89
Advance Information on S29GL-P Hardware Reset
(RESET#) and Power-up Sequence . . . . . . . . . . . 90
Table 18. Hardware Reset (RESET#) ....................................90
Figure 21. Reset Timings .................................................... 90
Table 19. Power-Up Sequence Timings .................................91
Figure 22. Power-On Reset Timings...................................... 91
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 92
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
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