參數(shù)資料
型號: S29GL128N10TAIV13
廠商: SPANSION LLC
元件分類: PROM
英文描述: 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology
中文描述: 8M X 16 FLASH 3V PROM, 100 ns, PDSO56
封裝: MO-142BEC, TSOP-56
文件頁數(shù): 66/100頁
文件大?。?/td> 952K
代理商: S29GL128N10TAIV13
64
S29GL-N MirrorBit Flash Family
S29GL-N_00_B3 October 13, 2006
D a t a S h e e t
Table 13. Sector Protection Commands (x16)
Command Sequence
( Notes)
Command Set Entry (
5
)
Program (
6
)
Read (
6
)
Command Set Exit (
7
)
Command Set Entry (
5
)
Program (
8
)
Read (
9
)
Unlock (
10
)
Command Set Exit (
7
)
Command Set Entry (
5
)
PPB Program (
11
)
All PPB Erase (
11
,
12
)
PPB Status Read
Command Set Exit (
7
)
Global
Volatile Sector
Protection
Freeze
(PPB Lock)
Command Set Exit (
7
)
Command Set Entry (
5
)
DYB Set
DYB Clear
DYB Status Read
Command Set Exit (
7
)
C
Bus Cycles ( Notes
1
4
)
Third
Addr
Data
555
40
First
Second
Fourth
Addr
Fifth
Sixth
Seventh
Addr
Addr
555
XX
00
XX
555
XX
XXX
00
XX
555
XX
XX
SA
XX
555
XX
XXX
XX
555
XX
XX
SA
XX
Data
AA
A0
Data
90
AA
A0
PWD0
25
90
AA
A0
80
RD(0)
90
AA
A0
RD(0)
90
AA
A0
A0
RD(0)
90
Addr
2AA
XXX
Data
55
Data
Data
Addr
Data
Addr
Data
Data
Lock
Register
Bits
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
2
3
2
2
1
2
XX
2AA
PWAx
01
00
XX
2AA
SA
00
00
55
Password
Protection
555
60
PWDx
PWD1
03
00
55
00
30
02
00
PWD2
PWD0
03
01
PWD3
PWD1
02
PWD2
03
PWD3
00
29
Non-Volatile
Sector
Protection (PPB)
555
C0
XX
2AA
XX
00
55
00
Command Set Entry (
5
)
PPB Lock Bit Set
PPB Lock Bit Status Read
555
50
XX
2AA
SA
SA
00
55
00
01
Volatile Sector
Protection
(DYB)
555
E0
XX
00
Legend:
X = Don’t care.
RA = Address of the memory location to be read.
SA = Sector Address. Any address that falls within a specified sector.
See Tables
2
4
for sector address ranges.
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If
unprotected, DQ0 = 1.
Notes:
1.
2.
3.
All values are in hexadecimal.
Shaded cells indicate read cycles.
Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
4.
5.
6.
No unlock or command cycles required when bank is reading
array data.
Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
Entire two bus-cycle sequence must be entered for each portion
of the password.
Full address range is required for reading password.
10. Password may be unlocked or read in any order. Unlocking
requires the full password (all seven cycles).
11. ACC must be at V
IH
when setting PPB or DYB.
12. “All PPB Erase” command pre-programs all PPBs before erasure
to prevent over-erasure.
7.
8.
9.
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