
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
41
Pin Name
Type
Pin
No.
Function
ID[1]
ID[2]
ID[3]
ID[4]
ID[5]
ID[6]
ID[7]
ID[8]
ID[9]
ID[10]
ID[11]
ID[12]
ID[13]
ID[14]
ID[15]
ID[16]
ID[17]
ID[18]
ID[19]
ID[20]
ID[21]
ID[22]
ID[23]
ID[24]
ID[25]
ID[26]
ID[27]
ID[28]
Output AA5
Y6
AA20
T19
R19
P20
G22
G21
Y2
W2
G4
H2
P21
P22
A12
D12
U2
V4
D11
A11
M19
L19
D10
A10
J1
H4
B10
C10
Ingress Data (ID[1:28]).
Each ID[x] signal contains
the recovered data stream which may have been
passed through the elastic store.
When the Clock Slave ingress modes are active, the
ID[x] stream has passed through the elastic store and
is aligned to the common ingress timing. In this mode
ID[x] is updated on the active edge of CICLK.
When the Clock Master ingress modes are active, ID[x]
is aligned to the receive line timing and is updated on
the active edge of the associated ICLK[x].
In E1 mode only ID[1:21] are used.
ID[1,5,9,13,17,21,25] share pins with the H-MVIP data
signals MVID[1:7]. ID[2,6,10,14,18,22,26] share pins
with the H-MVIP CAS signals CASID[1:7]. ID[1] shares
a pin with the DS3 system interface signal RDATO.
ID[2] shares a pin with the DS3 system interface signal
ROVRHD. ID[15,16,19,20,23,24,27,28] shares pins
with the SBI interface bus SDDATA[7:0].