
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER  WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
261
Figure 71
- Egress 8.192 Mbps H-MVIP Link Timing
CMV8MCLK
(16 MHz)
CMVFPB
MVED[x]
CASED[x]
CCSED
B8
B1
B2
B3
B4
B5
B6
B7
B8
B1
TS 127
TS 0
TS 1
CMVFPC
(4 MHz)
13.9 Ingress H-MVIP Link Timing
The timing relationship of the common 8M H-MVIP clock, CMV8MCLK, frame
pulse clock, CMVFPC, data, MVID[x], CASID[x] or CCSID, and frame pulse,
CMVFPB, signals of a link configured for 8.192 Mbps H-MVIP operation with a
type 0 frame pulse is shown in Figure 72.  The falling edges of each CMVFPC
are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbps H-
MVIP operation.  The TEMUX samples CMVFPB low on the falling edge of
CMVFPC and references this point as the start of the next frame.  The TEMUX
updates the data provided on MVID[x], CASID[x] and CCSID on every second
falling edge of CMV8MCLK as indicated for bit 2 (B2) of time-slot 1 (TS 1) in
Figure 72.  The first bit of the next frame is updated on MVID[x], CASID[x] and
CCSID on the falling CMV8MCLK clock edge for which CMVFPB is also sampled
low.  B1 is the most significant bit and B8 is the least significant bit of each octet.
Figure 72
- Ingress 8.192 Mbps H-MVIP Link Timing
CMV8MCLK
(16 MHz)
CMVFPB
MVID[x]
CASID[x]
CCSID
B8
B1
B2
B3
B4
B5
B6
B7
B8
B1
TS 127
TS 0
TS 1
CMVFPC
(4 MHz)