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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
268
Figure 85
- T1 Ingress Interface Clock Master: NxChannel Mode
ID[x]
ICLK[x]
1 2 3 4 5 6 7 8
Don't Care
1 2 3 4 5 6 7 8
IFP[x]
Figure 86
- E1 Ingress Interface Clock Master: NxChannel Mode
ID[x]
ICLK[x]
1 2 3 4 5 6 7 8
Don't Care
1 2 3 4 5 6 7 8
IFP[x]
Timeslot 31
Timeslot 1
The IMODE[1:0] bits in the T1/E1 Ingress Serial Interface Mode Select register
are programmed to select NxChannel mode. The RPSC ingress control bytes
are programmed to extract the desired channels. In Figure 85, the ingress
control bytes for T1 channels 2 and 24 are extracted. In Figure 86, the ingress
control bytes for E1 channels 31 and 1 are extracted. ICLK[x] is gapped so that it
is only active for those channels with the associated DTRKC bit set to 0. If either
IMFP or ALTIFP is set, then IFP[x] will pulse only during the appropriate frames.
When the IDE bit in the T1/E1 Serial Interface Configuration register bit is set,
then ID[x] is updated on the rising edge of ICLK[x] and the functional timing is
described by with ICLK[x] inverted.
Figure 87
- T1 and E1 Ingress Interface Clock Master: Clear Channel
Mode
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ICLK[x]
I D[x]
8
The Ingress Interface is configured for the Clock Slave: Clear Channel mode by
writing to IMODE[1:0] in the T1/E1 Ingress Serial Interface Mode Select register.
ID[x] is updated on the falling edge of the ICLK[x] input. When the IDE bit in the
T1/E1 Serial Interface Configuration register is set to logic 1, then ID[x] is