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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
112
9.32.3 DS3 Desynchronizer
The Desynchronizer monitors the Elastic Store level to control the de-stuffing
algorithm to avoid overflow and underflow conditions. The Desynchronizer
assumes either a 51.84 MHz clock (provided internally) or a 44.928 MHz clock
(provided via input CLK52M).
When using a 44.928 MHz CLK52M clock, the DS3 clock is generated using a
fixed 8 KHz interval. The 8KHz interval is subdivided into 9 rows. Each row
contains either 621 or 622 clock periods. The DS3RICLK contains 624 pulses at
72KHz (9*8KHZ). To generate 621 pulses, a gap pattern of 207 clocks + 1 clock
gap + 207 clocks + 1 clock gap + 207 clocks + 1 clock gap is used. To generate
622 pulses, a gap pattern of 207 clocks + 1 clock gap + 207 clocks + 1 clock gap
+ 208 clocks is used.
When using a 51.84 MHz CLK52M clock, the DS3 clock is generated using
similar gapping patterns. To generate 621 pulses per row, a gapping pattern of
63 * (7 clocks + 1 clock gap) + 36 * (5 clocks + 1 clock gap) is used. To generate
622 pulses per row, a gapping pattern of 63 * (7 clocks + 1 clock gap) + 35 * (5
clocks + 1 clock gap) + 6 clocks is used.
Table 8 illustrates the gap patterns used to generate the desynchronized DS3
clock under the normal, DS3 AIS, faster and slower status. The faster pattern is
used to drain the elastic store to avoid overflows. The slower pattern is used to
allow the elastic store to fill to avoid underflows.