
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER  WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
252
Figure 60
- Framer Mode DS3 Receive Output Stream
RDATO
INFO
84
RFPO/RMFPO
INFO
84
INFO
83
INFO
82
X
1
INFO
2
INFO
1
X
2
INFO
1
INFO
2
INFO
3
INFO
84
INFO
82
INFO
83
F
4
INFO
82
INFO
83
ROVRHD
RSCLK
Figure 61
- Framer Mode DS3 Receive Output Stream with RGAPCLK
RGAPCLK
RDATO
INFO
84
INFO
84
INFO
83
INFO
82
INFO
2
INFO
1
INFO
1
INFO
2
INFO
3
INFO
84
INFO
82
INFO
83
INFO
82
INFO
83
The DS3 Framer Only Mode Receive Output Stream diagram (Figure 60) shows
the format of the outputs RDATO, RFPO/RMFPO, RSCLK ROVRHD when the
OPMODE[1:0] bits are set to “DS3 Framer Only mode” in the Global
Configuration register.  Figure 60 shows the data streams when the TEMUX is
configured for the DS3 receive format.  If the RXMFPO bit in the DS3 Master
Unchannelized Interface Options register is logic 0, RFPO is valid and will pulse
high for one RSCLK cycle on first bit of each M-subframe with alignment to the
RDATO data stream.  If the RXMFPO register bit is a logic 1 (as shown Figure
60), RMFPO is valid and will pulse high on the X1 bit of the RDATO data output
stream.  ROVRHD will be high for every overhead bit position on the RDATO
data stream.  Figure 61 shows the output data stream with RGAPCLK in place of
RSCLK when the RXGAPEN bit in the DS3 Master Unchannelized Interface
Options register set to logic 1.  RGAPCLK remains high during the overhead bit
positions.