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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
11
Provides diagnostic features to allow the generation of line code violation
error events, parity error events, framing bit error events, and when enabled
for the C-bit parity application, C-bit parity error events, and far end block
error (FEBE) events.
Supports insertion of bit-oriented codes in the C-bit parity far end alarm and
control channel.
Optionally inserts the C-bit parity path maintenance data link with an integral
HDLC transmitter. Supports polled and interrupt-driven operation.
Provides programmable pseudo-random test sequence generation (up to
232-1 bit length sequences conforming to ITU-T O.151 standards) or any
repeating pattern up to 32 bits. The test pattern can be framed or unframed.
Diagnostic abilities include single bit error insertion or error insertion at bit
error rates ranging from 10-1 to 10-7.
M23 Multiplexer Section:
Multiplexes 7 DS2 bit streams into a single M23 format DS3 bit stream.
Performs required bit stuffing/destuffing including generation and
interpretation of C-bits.
Includes required FIFO buffers for rate adaptation in the multiplex path.
Allows insertion and detection of per DS2 payload loopback requests
encoded in the C-bits to be activated under microprocessor control.
Internally generates DS2 clock for use in integrated M13 or C-bit parity
multiplex applications. Alternatively accepts external DS2 clock reference.
Allows per DS2 alarm indication signal (AIS) to be activated or cleared for
either direction under microprocessor control.
Allows DS2 alarm indication signal (AIS) to be activated or cleared in the
demultiplex direction automatically upon loss of DS3 frame alignment or
signal.
Supports C-bit parity DS3 format.