
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER  WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
249
13 
FUNCTIONAL TIMING
13.1 DS3 Line Side Interface Timing
All functional timing diagrams assume that polarity control is not being applied to
input and output data and clock lines (i.e. polarity control bits in the TEMUX
registers are set to their default states).
Figure 54
- Receive Bipolar DS3 Stream
RPOS
RNEG
3 consec 0s
LCV
RCLK
The Receive Bipolar DS3 Stream diagram (Figure 54) shows the operation of the
TEMUX while processing a B3ZS encoded DS3 stream on inputs RPOS and
RNEG.  It is assumed that the first bipolar violation (on RNEG) illustrated
corresponds to a valid B3ZS signature.  A line code violation is declared upon
detection of three consecutive zeros in the incoming stream, or upon detection of
a bipolar violation which is not part of a valid B3ZS signature.
Figure 55
- Receive Unipolar DS3 Stream
RCLK
RDAT
X1 BIT
RLCV
X2 BIT
INFO 84
C BIT
INFO 1
INFO 2
INFO 3
INFO 4
INFO 5
OR P OR M BIT
OR F BIT
INFO 84
INFO 1
LCV INDICATION
The Receive Unipolar DS3 Stream diagram (Figure 55) shows the complete DS3
receive signal on the RDAT input.  Line code violation indications, detected by an
upstream B3ZS decoder, are indicated on input RLCV.  RLCV is sampled each
bit period.  The PMON Line Code Violation Event Counter is incremented each
time a logic 1 is sampled on RLCV.