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| 型號： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數： | 9/94頁 |
| 文件大?。?/td> | 892K |
| 代理商： | PENTIUM II PROCESSOR |
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E
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
9
2.0.
ELECTRICAL SPECIFICATIONS
2.1.
The Pentium
II Processor
System Bus and V
REF
Most of the Pentium II processor signals use a
variation
of the low voltage Gunning Transceiver
Logic (GTL) signaling technology.
The Pentium II processor System Bus specification
is similar to the GTL specification, but has been
enhanced to provide larger noise margins and
reduced
ringing.
The
accomplished by increasing the termination voltage
level and controlling the edge rates. Because this
specification is different from the standard GTL
specification, it is referred to as
GTL+
in this
document.
For
more
specifications, see AP-585, Pentium
II Processor
GTL+ Guidelines(Order Number 243330).
improvements
are
information
on
GTL+
The GTL+ signals are open-drain and requires
termination to a supply that provides the high signal
level. The GTL+ inputs use differential receivers
which require a reference signal (V
REF
). Termination
(usually a resistor at each end of the signal trace) is
used to pull the bus up to the high voltage level and
to control reflections on the transmission line. V
REF
is
used by the receivers to determine if a signal is a
logical 0 or a logical 1, and is generated on the
S.E.C. cartridge for the processor core. The
processor contains termination resistors that provide
termination for one end of the Pentium II processor
System Bus. Termination (usually a resistor on each
end of the signal trace) is used to pull the bus up to
the high voltage level and to control reflections on the
transmission line. See Table 9 for the bus termination
voltage specifications for GTL+ and the Pentium
II
Processor Developer’s Manual(Order Number
243341) for the GTL+ bus specification. V
REF
is
generated on the S.E.C. cartridge for the Pentium II
processor core. Local V
REF
copies should be
generated on the motherboard for all other devices
on the GTL+ System Bus. Figure 2 is a schematic
representation of GTL+ bus topology with the
Pentium II processor.
The GTL+ bus depends on incident wave switching.
Therefore timing calculations for GTL+ signals are
based on
flight time
as opposed to capacitive
deratings. Analog signal simulation of the Pentium II
processor System Bus including trace lengths is
highly recommended when designing a system with
a heavily loaded GTL+ bus. See Intel’s World Wide
Web page (http://www.intel.com) to download the
buffer models, Pentium
II Processor I/O Buffer
Models, BIS Format (Electronic Form).
2.2.
Clock Control and Low Power
States
The Pentium II processor allows the use of
AutoHALT, Stop-Grant, Sleep and Deep Sleep states
to reduce power consumption by stopping the clock
to internal sections of the processor, depending on
each particular state. See Figure 3 for a visual
representation of the Pentium II processor low power
states.
For the processor to fully realize the low current
consumption of the Stop-Grant, Sleep and Deep
Sleep states, a Model Specific Register (MSR) bit
must be set. For the MSR at 02AH (Hex), bit 26 must
be set to a ‘1’ (this is the power on default setting) for
the processor to stop all internal clocks during these
modes. For more information, see the Pentium
II
Processor Developer’s Manual(Order Number
243341).
Pentium
II
Processor
No Stubs
ASIC
ASIC
Pentium II
Processor
000916
Figure 2. GTL+ Bus Topology
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