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參數資料
| 型號： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數： | 11/94頁 |
| 文件大?。?/td> | 892K |
| 代理商： | PENTIUM II PROCESSOR |
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PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
11
FLUSH# will be serviced during AutoHALT state and
the processor will return to the AutoHALT state.
The system can generate a STPCLK# while the
processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt,
the processor will return execution to the HALT state.
2.2.3.
STOP-GRANT STATE — STATE 3
The Stop-Grant state on the processor is entered
when the STPCLK# signal is asserted.
Since the GTL+ signal pins receive power from the
System Bus, these pins should not be driven
(allowing the level to return to V
TT
) for minimum
power drawn by the termination resistors in this state.
In addition, all other input pins on the System Bus
should be driven to the inactive state.
FLUSH# will be serviced during Stop-Grant state and
the processor will return to the Stop-Grant state.
RESET# will cause the processor to immediately
initialize itself, but the processor will stay in Stop-
Grant state. A transition back to the Normal state will
occur with the deassertion of the STPCLK# signal.
A transition to the HALT/Grant Snoop state will occur
when the processor detects a snoop on the System
Bus (see Section 2.2.4.). A transition to the Sleep
state (see Section 2.2.5.) will occur with the assertion
of the SLP# signal.
While in the Stop-Grant state, SMI#, INIT# and
LINT[1:0] will be latched by the processor, and only
serviced when the processor returns to the Normal
state. Only one occurrence of each event will be
recognized upon return to the Normal state.
2.2.4.
HALT/GRANT SNOOP STATE —
STATE 4
The processor will respond to snoop transactions on
the Slot 1 processor System Bus while in Stop-Grant
state or in AutoHALT Power Down state. During a
snoop transaction, the processor enters the
HALT/Grant Snoop state. The processor will stay in
this state until the snoop on the Slot 1 processor
System Bus has been serviced (whether by the
processor or another agent on the Slot 1 by the
processor or another agent on the Slot 1 processor
System Bus). After the snoop is serviced, the
processor will return to the Stop-Grant state or
AutoHALT Power Down state, as appropriate.
2.2.5.
SLEEP STATE — STATE 5
The Sleep state is a very low power state in which
the processor maintains its context, maintains the
phase-locked loop (PLL), and has stopped all internal
clocks. The Sleep state can only be entered from
Stop-Grant state. Once in the Stop-Grant state, the
SLP# pin can be asserted, causing the processor to
enter the Sleep state. The SLP# pin is not recognized
in the Normal or AutoHALT states.
Snoop events that occur while in Sleep state or
during a transition into or out of Sleep state will cause
unpredictable behavior.
In the Sleep state, the processor is incapable of
responding to snoop transactions or latching interrupt
signals. No transitions or assertions of signals (with
the exception of SLP# or RESET#) are allowed on
the system bus while the processor is in Sleep state.
Any transition on an input signal before the processor
has returned to Stop Grant state will result in
unpredictable behavior.
If RESET# is driven active while the processor is in
the Sleep state, and held active as specified in the
RESET# pin specification, then the processor will
reset itself, ignoring the transition through Stop-Grant
state. If RESET# is driven active while the processor
is in the Sleep state, the SLP# and STPCLK# signals
should be deasserted immediately after RESET# is
asserted to ensure the processor correctly executes
the Reset sequence.
While in the Sleep state, the processor is capable of
entering its lowest power state, the Deep Sleep state,
by stopping the BCLK input. (see Section 2.2.6.)
Once in the Sleep or Deep Sleep states, the SLP#
pin can be deasserted if another asynchronous
System Bus event occurs. The SLP# pin has a
minimum assertion of one BCLK period.
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