參數(shù)資料
型號(hào)： pentium II processor
廠商： Intel Corp.
英文描述： 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器)
中文描述： 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬(wàn)和333兆赫茲32位處理器）
文件頁(yè)數(shù)： 41/94頁(yè)
文件大?。?/td> 892K
代理商： PENTIUM II PROCESSOR
E
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
41
3.3.2.
RINGBACK SPECIFICATION
Ringback refers to the amount of reflection seen after
a signal has switched. The ringback specification is
the voltage that the signal rings back to after
achieving its maximum absolute value.
(See
Figure 18 for an illustration of ringback.) Excessive
ringback can cause false signal detection or extend
the propagation delay. The ringback specification
applies to the input pin of each receiving agent.
Violations of the signal Ringback specification are not
allowed under any circumstances for the non-GTL+
signals.
Ringback can be simulated with or without the input
protection diodes that can be added to the input
buffer model. However, signals that reach the
clamping voltage should be evaluated further. See
Table 19 for the signal ringback specifications for
non-GTL+ signals.
3.3.3.
SETTLING LIMIT GUIDELINE
Settling limit defines the maximum amount of ringing
at the receiving pin that a signal must reach before its
next transition. The amount allowed is 10 percent of
the total signal swing (V
HI
–V
LO
) above and below its
final value. A signal should be within the settling limits
of its final value, when either in its high state or low
state, before it transitions again.
Signals that are not within their settling limit before
transitioning are at risk of unwanted oscillations
which could jeopardize signal integrity. Simulations to
verify settling limit may be done either with or without
the input protection diodes present. Violation of the
settling limit guideline is acceptable if simulations of 5
to 10 successive transitions do not show the
amplitude of the ringing increasing in the subsequent
transitions.
Table 19. Signal Ringback Specifications for Non-GTL+ Signals
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Figure
Non-GTL+ Signals
0
→
1
2.0 V
17
Non-GTL+ Signals
1
→
0
0.7 V
17
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